| Part Number | dsPIC33CK32MP202 |
| Manufacturer | Microchip |
| Title | 16-Bit Digital Signal Controllers |
| Description | dsPIC33CK256MP508 FAMILY 28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating ... |
| Features |
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| File Size | 3.68MB |
| Datasheet |
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dsPIC33CK32MP206 : dsPIC33CK256MP508 FAMILY 28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating Conditions • 3.0V to 3.6V, -40°C to +85°C, DC to 100 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS Core: 16-Bit dsPIC33CK CPU • 32-256 Kbytes of Program Flash with ECC and 8-24K RAM • Fast 6-Cycle Divide • LiveUpdate • Code Efficient (C and Assembly) Architecture • 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle, Mixed-Sign MUL Plus Hardware Divide • 32-Bit Multiply Support • Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Interrupt Handling • Zero Overhead L.
dsPIC33CK32MP205 : dsPIC33CK256MP508 FAMILY 28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating Conditions • 3.0V to 3.6V, -40°C to +85°C, DC to 100 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS Core: 16-Bit dsPIC33CK CPU • 32-256 Kbytes of Program Flash with ECC and 8-24K RAM • Fast 6-Cycle Divide • LiveUpdate • Code Efficient (C and Assembly) Architecture • 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle, Mixed-Sign MUL Plus Hardware Divide • 32-Bit Multiply Support • Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Interrupt Handling • Zero Overhead L.
dsPIC33CK32MP203 : dsPIC33CK256MP508 FAMILY 28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD) Operating Conditions • 3.0V to 3.6V, -40°C to +85°C, DC to 100 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS Core: 16-Bit dsPIC33CK CPU • 32-256 Kbytes of Program Flash with ECC and 8-24K RAM • Fast 6-Cycle Divide • LiveUpdate • Code Efficient (C and Assembly) Architecture • 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle, Mixed-Sign MUL Plus Hardware Divide • 32-Bit Multiply Support • Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Interrupt Handling • Zero Overhead L.