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74LS191

Motorola
Part Number 74LS191
Manufacturer Motorola
Description PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS
Published Jul 18, 2016
Detailed Description PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54 / 74LS190 is a synchronous UP...
Datasheet PDF File 74LS191 PDF File

74LS191
74LS191

Overview
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421) Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16 Binary Counter.
State changes of the counters are synchronous with the LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous Parallel Load (PL) input overrides counting and loads the data present on the Pn inputs into the flip-flops, which makes it possible to use the circuits as programmable counters.
A Count Enable (CE) input serves as the carry / borrow input in multi-stage counters.
An Up / Down Count Control (U/D) input determines whether a circuit counts up or down.
A Terminal Count (TC) output and a Ripple Clock (RC) output provide overflow/underflow indication and make possible a variety of methods for generating carry / borrow signals in multistage counter applications.
• Low Power .
.
.
90 mW Typical Dissipation • High Speed .
.
.
25 MHz Typical Count Frequency • Synchronous Counting • Asynchronous Parallel Load • Individual Preset Inputs • Count Enable and Up/ Down Control Inputs • Cascadable • Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 P0 15 CP 14 RC 13 TC 12 PL 11 P2 10 P3 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
1 P1 2 Q1 3 Q0 4 CE 5 U/D 6 Q2 7 Q3 8 GND PIN NAMES LOADING (Note a) HIGH LOW CE Count Enable (Active LOW) Input 1.
5 U.
L.
0.
7 U.
L.
CP Clock Pulse (Active HIGH going edge) Input 0.
5 U.
L.
0.
25 U.
L.
U / D Up/Down Count Control Input 0.
5 U.
L.
0.
25 U.
L.
PL Parallel Load Control (Active LOW) Input 0.
5 U.
L.
0.
25 U.
L.
Pn Parallel Data Inputs Qn Flip-Flop Outputs (Note b) RC Ripple Clock Output (Note b) 0.
5 U.
L.
10 U.
L.
10 U.
L.
0.
25 U.
L.
5 (2.
5) U.
L.
5 (2.
5) U.
L.
TC Terminal Count Output (Note b) 10 U.
L.
5 (2.
5) U.
L.
NOTES: a.
1 TTL Unit Load (U.
L.
) = 40 µA HIGH/1.
6 mA LOW.
b.
The Outp...


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