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54LS256

Part Number	54LS256
Manufacturer	National Semiconductor
Description	Dual 4-Bit Addressable Latch
Published	Aug 1, 2016
Detailed Description	54LS256 DM74LS256 Dual 4-Bit Addressable Latch June 1989 54LS256 DM74LS256 Dual 4-Bit Addressable Latch General Descr...
Datasheet	54LS256 PDF File

Overview

54LS256 DM74LS256 Dual 4-Bit Addressable Latch June 1989 54LS256 DM74LS256 Dual 4-Bit Addressable Latch General Description The ’LS256 is a dual 4-bit addressable latch with common control inputs these include two Address inputs (A0 A1) an active LOW enable input (E) and an active LOW Clear input (CL) Each latch has a Data input (D) and four outputs (Q0 – Q3) When the Enable (E) is HIGH and the Clear input (CL) is LOW all outputs (Q0–Q3) are LOW Dual 4-channel demultiplexing occurs when the CL and E are both LOW When CL is HIGH and E is LOW the selected output (Q0 – Q3) determined by the Address inputs follows D When the E goes HIGH the contents of the latch are stored When operating in the addressable latch mode (E e LOW CL e HIGH) changing more than one bit of the Address (A0 A1) could impose a transient wrong address Therefore this should be done only while in the memory mode (E e CL e HIGH) Features Y Serial-to-parallel capability Y Output from each storage bit available Y Random (addressable) data entry Y Easily expandable Y Active low common clear Connection Diagram Logic Symbol Dual-In-Line Package TL F 9823–1 Order Number 54LS256DMQB 54LS256FMQB or DM74LS256N See NS Package Number J16A N16E or W16A VCC e Pin 16 GND e Pin 8 Pin Names A0 A1 Da Db E CL Q0a – Q3a Q0b – Q3b Description Common Address Inputs Data Inputs Common Enable Input (Active LOW) Conditional Clear Input (Active LOW) Side A Latch Outputs Side B Latch Outputs TL F 9823 – 2 C1995 National Semiconductor Corporation TL F 9823 RRD-B30M115 Printed in U S A Truth Table Inputs Outputs CL E A0 A1 Q0 Q1 Q2 Q3 LHX X L L L L LLL L D L L L L LH L L D L L LLL H L L D L L LH H L L L D HHX X Qtb1 Qtb1 Qtb1 HLL L D Qtb1 Qtb1 HLH L Qtb1 D Qtb1 HLL H Qtb1 Qtb1 D H LH H Qtb1 Qtb1 Qtb1 tb1 e Bit time before address change or rising edge of E H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Mode Selection Qtb1 Qtb1 Qtb1 Qtb1 D ...

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