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MC100E143

Part Number MC100E143
Manufacturer Motorola
Title 9-BIT HOLD REGISTER
Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9ĆBit Hold Register The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications ...
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MC100E141 : The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0 − D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated. The select pins, SEL0 and SEL1, select one of four modes of operation: Load, Hold, Shift Left, Shift Right, according to the Function Table. Input data is accepted a set-up time before the positive clock edge. A HIGH on the Master Reset (MR) pin asynchronously resets all.

MC100E141 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8ĆBit Shift Register The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0 – D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated. • 700MHz Min. Shift Frequency • 8-Bit • Full-Function, Bi-Directional • Asynchronous Master Reset • Pin-Compatible with E241 • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors MC10E14.

MC100E142 : The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 − D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated. The SEL (Select) input pin is used to switch between the two modes of operation − SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accom.

MC100E142 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9ĆBit Shift Register The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 – D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated. • 700MHz Min. Shift Frequency • 9-Bit for Byte-Parity Applications • Asynchronous Master Reset • Dual Clocks • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors The SEL (Select) i.

MC100E143 : The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 − D8 accepting parallel input data. The SEL (Select) input pin is used to switch between the two modes of operation − HOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero. The 100 Series contains temperature compensation. Features • 700 MHz Min. Operating Frequency • 9-Bit for Byte-Parity Applications • Asynchronous Master Reset • Dual Clocks • PECL Mode Operating Range: ♦ VCC= 4.2 V.




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