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MC100LVEL51 Datasheet PDF

Motorola
Part Number MC100LVEL51
Manufacturer Motorola
Title Differential Clock D Flip-Flop
Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential Clock D FlipĆFlop The MC100LVEL51 is a differential clock D flip-flop with reset. The device i...
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MC100LVEL51 MC100LVEL51 MC100LVEL51




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MC100LVEL01 : PIN D0–D3 Q FUNCTION Data Inputs Data Outputs DC CHARACTERISTICS Symbol Characteristic IEE VEE IIH Power Supply Current Power Supply Voltage Input HIGH Current –40°C 0°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit 15 20 15 20 15 20 17 22 mA –3.0 –3.3 –3.8 –3.0 –3.3 –3.8.

MC100LVEL01 : The MC100LVEL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in AC performance. Features • 370 ps Propagation Delay • High Bandwidth Output Transitions • ESD Protection: ♦ 2 kV Human Body Model ♦ 200 V Machine Model • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V • Internal Input Pulldown Resistors • Q Output will Default LOW with All Inputs Open or at VEE • Meets o.

MC100LVEL05 : The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally suited for those applications which require the ultimate in AC performance at low voltage power supplies. Because a negative 2-input NAND is equivalent to a 2-input OR function, the differential inputs and outputs of the device allows the LVEL05 to also be used as a 2-input differential OR/NOR gate. Features • 340 ps Propagation Delay • High Bandwidth Output Transitions • ESD Protection: ♦ 4 kV Human Body Mode ♦ 200 V Machine Model •.

MC100LVEL05 : PIN D0, D1 Q FUNCTION Data Inputs Data Outputs 1/97 © Motorola, Inc. .

MC100LVEL11 : PIN D Q0, Q1 FUNCTION Data Inputs Data Outputs DC CHARACTERISTICS (VEE.

MC100LVEL11 : The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the LVEL11 is ideally suited for those applications which require the ultimate in AC performance. The differential inputs of the LVEL11 employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open (pulled to VEE) the Q outputs will go LOW. Features • 330 ps Propagation Delay • 5 ps Skew Between Outputs • High Bandwidth Output Transitions • The 100 Series Contains Temperature Compensation • PECL Mode Operating R.

MC100LVEL12 : PIN D0, D1 Qa, Qb FUNCTION Data Inputs Data Outputs DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND) –40°C 0°C 25°C 85°C Symbol Characteristic Min Typ Max Min T.

MC100LVEL12 : The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply. With propagation delays equivalent to the EL12, the LVEL12 is ideally suited for those applications which require the ultimate in AC performance in a low voltage environment. Features http://onsemi.com MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 8 1 TSSOP−8 DT SUFFIX CASE 948R 8 KVL12 ALYW G 1 • 445 ps Propagation Delay • Dual Outputs for 25 W Drive Applications • ESD Protection: 4 kV Human Body Model, 200 V Machine Model 8.

MC100LVEL13 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 1:3 Fanout Buffer The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer. The MC100EL13 is pin and functionally equivalent to the MC100LVEL13 but is specified for operation at the standard 100E ECL voltage supply. The Low Output–Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 and the Q output will go LOW. • Differential Inputs and Outputs • 20–Lead SOIC Packaging • 500p.

MC100LVEL13 : The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer. The Low Output-Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 and the Q output will go LOW. Features • 500 ps Typical Propagation Delays • 50 ps Output-Output Skews • ESD Protection: 2 kV Human Body Model • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = .

MC100LVEL14 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1:5 Clock Distribution Chip The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or 3.0V to 3.8V). If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for.

MC100LVEL14 : The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of −3.0 V to −3.8 V ( or 3.0 V to 3.8 V). The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock i.

MC100LVEL16 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential Receiver The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a low voltage supply. The LVEL16 exhibits a wider CMR range than its EL16 counterpart. With output transition times and propagation delays comparable to the EL16 the LVEL16 is ideally suited for interfacing with high frequency sources at 3.3V supplies. The LVEL16 provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for the LVEL16 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to groun.

MC100LVEL16 : The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a 3.3 V supply. The LVEL16 exhibits a wider VIHCMR range than its EL16 counterpart. With output transition times and propagation delays comparable to the EL16 the LVEL16 is ideally suited for interfacing with high frequency sources at 3.3 V supplies. Under open input conditions, the Q input will be pulled down to VEE and the Q input will be biased to VCC/2. This condition will force the Q output low. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a sw.

MC100LVEL17 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA LowĆVoltage Quad Differential Receiver The MC100LVEL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a –3.3V or +3.3V supply voltage. The MC100EL17 is pin and functionally equivalent to the MC100LVEL17, but is specified for operation at the standard 100E ECL voltage supply. The LVEL17 provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for the LVEL17 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to ground via a 0.01µf .

MC100LVEL17 : The MC100LVEL17 is a 3.3 V ECL, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a −3.3 V or +3.3 V supply voltage. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing o.

MC100LVEL29 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual Differential Data and Clock D Flip-Flop With Set and Reset MC100LVEL29 MC100EL29 The MC100LVEL29 is a dual master–slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100EL29 is pin and functionally equivalent to the MC100LVEL29 but is specified for operation at the standard 100E ECL voltage supply. A VBB output is provided for AC coupling, refer to the interfacing section of the ECLinPS Data Book (DL140) for more information on AC coupling ECL signals. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input. The differential inp.




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