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74AHCT273

nexperia
Part Number 74AHCT273
Manufacturer nexperia
Description Octal D-type flip-flop
Published Apr 25, 2018
Detailed Description 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 4 — 23 September 2020 Product data ...
Datasheet PDF File 74AHCT273 PDF File

74AHCT273
74AHCT273

Overview
74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev.
4 — 23 September 2020 Product data sheet 1.
General description The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard No.
7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input.
The device is useful for applications where only the true output is required and the clock and master reset are common to all storage elements.
2.
Features • Balanced propagation delays • All inputs have Schmitt...


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