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74VHC08

nexperia
Part Number 74VHC08
Manufacturer nexperia
Description Quad 2-input AND gate
Published Jul 23, 2019
Detailed Description 74VHC08; 74VHCT08 Quad 2-input AND gate Rev. 2 — 8 April 2020 Product data sheet 1. General description The 74VHC08; 7...
Datasheet PDF File 74VHC08 PDF File

74VHC08
74VHC08

Overview
74VHC08; 74VHCT08 Quad 2-input AND gate Rev.
2 — 8 April 2020 Product data sheet 1.
General description The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard JESD7-A.
The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
2.
Features and benefits • Balanced propagation delays • All inputs have a Schmitt-trigger action • Inputs accepts voltages higher than VCC • Input levels: • The 74VHC08 operates with CMOS logic levels • The 74VHCT08 operates with TTL logic levels • ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101C exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74VHC08D 74VHCT08D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.
9 mm 74VHC08PW 74VHCT08PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
4 mm 74VHC08BQ 74VHCT08BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5 × 3 × 0.
85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4.
Functional diagram 1 & 3 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 2Y 6 3Y 8 4Y 11 mna222 Fig.
1.
Logic symbol 4 & 6 5 9 & 8 10 12 & 11 13 mna223 Fig.
2.
IEC logic symbol 5.
Pinning information 74VHC08; 74VHCT08 Quad 2-input AND gate A Y B mna221 Fig.
3.
Logic diagram (one gate) 5.
1.
Pinning 74VHC08 74VHCT08 1A 1 1B 2 14 VCC 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y 001aak040 Fig.
4.
Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) 74VHC08 74VHCT08 1 1A 14 VCC terminal 1 index area 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND(1) 13 4B 12 4A 11 4Y 10 3B 9 3A GND ...


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