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74HC112

nexperia
Part Number 74HC112
Manufacturer nexperia
Description Dual JK flip-flop
Published Jul 23, 2019
Detailed Description 74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Rev. 4 — 11 January 2021 Product data s...
Datasheet PDF File 74HC112 PDF File

74HC112
74HC112

Overview
74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Rev.
4 — 11 January 2021 Product data sheet 1.
General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop.
It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs.
It also has complementary nQ and nQ outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input.
The J and K inputs control the state changes of the flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
2.
Features and benefits • Input levels: • For 74HC112: CMOS level • For 74HCT11...


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