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NTE74LS78

NTE
Part Number NTE74LS78
Manufacturer NTE
Description Dual J-K Flip-Flop
Published Nov 15, 2019
Detailed Description NTE74LS78 Integrated Circuit TTL − Dual J−K Flip−Flop with Preset, Common Clock and Common Clear Description: The NTE74...
Datasheet PDF File NTE74LS78 PDF File

NTE74LS78
NTE74LS78

Overview
NTE74LS78 Integrated Circuit TTL − Dual J−K Flip−Flop with Preset, Common Clock and Common Clear Description: The NTE74LS78 is a dual J−K flip−flop in a 14−Lead plastic DIP type package that contains two negative−edge−triggered flip−flops with individual J−K, preset inputs, and common clock and common clear inputs.
The logic levels at the J and K inputs may be allowed to change while the clock pulse is high and the flip−flop will perform according to the function table as long as minimum setup and hold times are observed.
The preset and clear are asynchronous active low inputs.
When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table.
Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC .
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7V Input Voltage .
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7V Operating Temperature Range, TA .
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0C to +70C Storage Temperature Range, Tstg .
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−65C to +150C Note 1.
Voltage values are with respect to network ground terminal.
Recommended Operating Conditions: Parameter Supply Voltage High−Level Input Voltage Low−Level Input Voltage High−Level Output Current Low−Level Output Current Clock Frequency Pulse Duration CLK High PRE or CLR Low Setup Time Before CLK  Data High or Low PRE or CLR Inactive Hold Time Data After CLK  Operating Temperature Range Symbol VCC VIH VIL IOH IOL fclock tw tsu th TA Min Typ Max Unit 4.
75 5.
0 5.
25 V 2− −V − − 0.
8 V − − −0.
4 mA − − 8 mA 0 − 30 MHz 20 − 25 − − ns − ns 20 − − ns 20 − − ns 0 − − ns 0 − +70 C Electrical Characteristics: (Note 2, Note 3) Parameter Input Clamp Voltage Hig...


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