Part Number  CD74HCT73 
Manufacturer  Texas Instruments 
Title  Dual JK FlipFlop 
Description  • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • B... 
Features 
Description
• Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range)  Standard Outputs . ... 
File Size  972.13KB 
Datasheet 

CD74HC00 : • Buffered Inputs • Typical Propagation Delay: CL = 15pF, TA = 25oC 7ns at VCC = 5V, • Fanout (Over Temperature Range)  Standard Outputs 10 LSTTL Loads  Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range 55oC to 125oC The CD54HC00, CD74HC00, CD54HCT00, and CD74HCT00 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family. Ordering Information •.
CD74HC02 : • Buffered Inputs • Typical Propagation Delay: CL = 15pF, TA = 25oC 7ns at VCC = 5V, • Fanout (Over Temperature Range)  Standard Outputs 10 LSTTL Loads  Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range 55oC to 125oC • Balanced Propagation Delay and Transition Times • Signiﬁcant Power Reduction Compared to LSTTL Logic ICs • HC Types  2V to 6V Operation  High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types  4.5V to 5.5V Operation  Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)  CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC02 and ’HCT02 .
CD74HC03 : • Buffered Inputs • Typical Propagation Delay: CL = 15pF, TA = 25oC 8ns at VCC = 5V, • Output Pullup to 10V • Fanout (Over Temperature Range)  Standard Outputs 10 LSTTL Loads  Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range 55oC to 125oC • Balanced Propagation Delay and Transition Times • Signiﬁcant Power Reduction Compared to LSTTL Logic ICs • HC Types  2V to 6V Operation  High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types  4.5V to 5.5V Operation  Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)  CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH .
CD74HC04 : • Buffered Inputs • Typical Propagation Delay: CL = 15pF, TA = 25oC 6ns at VCC = 5V, • Fanout (Over Temperature Range)  Standard Outputs 10 LSTTL Loads  Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range 55oC to 125oC • Balanced Propagation Delay and Transition Times • Signiﬁcant Power Reduction Compared to LSTTL Logic ICs • HC Types  2V to 6V Operation  High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types  4.5V to 5.5V Operation  Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)  CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The CD54HC04, CD5.
CD74HC08 : • Buffered Inputs • Typical Propagation Delay: CL = 15pF, TA = 25oC 7ns at VCC = 5V, • Fanout (Over Temperature Range)  Standard Outputs 10 LSTTL Loads  Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range 55oC to 125oC • Balanced Propagation Delay and Transition Times • Signiﬁcant Power Reduction Compared to LSTTL Logic ICs • HC Types  2V to 6V Operation  High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types  4.5V to 5.5V Operation  Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The CD54HC08, CD54HCT.
CD74HC08EP : .
CD74HC08Q1 : This device contains four independent 2input AND gates. Each gate performs the Boolean function Y = A ● B in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC08QM96Q1 SOIC (14) 8.70 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional pinout of the CD74HC08Q1 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safetycritical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74HC08Q1 SCLS512B – JUL.
CD74HC10 : This device contains three independent 3input NAND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC10M SOIC (14) 8.70 mm × 3.90 mm CD74HC10E PDIP (14) 19.30 mm × 6.40 mm CD54HC10F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y Functional Pinout An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safetycritical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74.
CD74HC107 : • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range)  Standard Outputs 10 LSTTL Loads  Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range 55oC to 125oC The ’HC107 and CD74HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These ﬂipﬂops have ind.
CD74HC109 : • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • TTAyp=ic2a5lofCMAX = 54MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range)  Standard Outputs 10 LSTTL Loads  Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range 55oC to 125oC The ’HC109 and ’HCT109 are dual JK ﬂipﬂops with set and reset. The ﬂipﬂop changes state with the positive transition of Clock (1CP and 2CP). The ﬂipﬂop is set and reset by activelow S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an.
CD74HC10E : This device contains three independent 3input NAND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC10M SOIC (14) 8.70 mm × 3.90 mm CD74HC10E PDIP (14) 19.30 mm × 6.40 mm CD54HC10F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y Functional Pinout An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safetycritical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74.
CD74HC10M : This device contains three independent 3input NAND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC10M SOIC (14) 8.70 mm × 3.90 mm CD74HC10E PDIP (14) 19.30 mm × 6.40 mm CD54HC10F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y Functional Pinout An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safetycritical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74.
CD74HC11 : This device contains three independent 3input AND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC11M SOIC (14) 8.70 mm × 3.90 mm CD74HC11E PDIP (14) 19.30 mm × 6.40 mm CD54HC11F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y Functional pinout CopyrighAtn©I2M0P21OTReTxaAsNInTsNtruOmTeInCtsEInactotrhpeoreatnedd of this data sheet addresses availability, warranty, changes, use iSnusbamfeittyDcorcituicmael anpt pFleiceadtbioancsk, 1 intellectual property m.
CD74HC112 : • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Set and Reset • Complementary Outputs • Buffered Inputs • TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range)  Standard Outputs 10 LSTTL Loads  Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range 55oC to 125oC • Balanced Propagation Delay and Transition Times • Signiﬁcant Power Reduction Compared to LSTTL Logic ICs • HC Types  2V to 6V Operation  High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types  4.5V to 5.5V Operation  Direct LSTTL Input Lo.
CD74HC11E : This device contains three independent 3input AND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC11M SOIC (14) 8.70 mm × 3.90 mm CD74HC11E PDIP (14) 19.30 mm × 6.40 mm CD54HC11F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y Functional pinout CopyrighAtn©I2M0P21OTReTxaAsNInTsNtruOmTeInCtsEInactotrhpeoreatnedd of this data sheet addresses availability, warranty, changes, use iSnusbamfeittyDcorcituicmael anpt pFleiceadtbioancsk, 1 intellectual property m.
CD74HC11M : This device contains three independent 3input AND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC11M SOIC (14) 8.70 mm × 3.90 mm CD74HC11E PDIP (14) 19.30 mm × 6.40 mm CD54HC11F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y Functional pinout CopyrighAtn©I2M0P21OTReTxaAsNInTsNtruOmTeInCtsEInactotrhpeoreatnedd of this data sheet addresses availability, warranty, changes, use iSnusbamfeittyDcorcituicmael anpt pFleiceadtbioancsk, 1 intellectual property m.
CD74HC123 : The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CX provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. Once triggered, the output pulse width may be extended by retriggering inputs A and B..