DatasheetsPDF.com

9DBL0255

Part Number	9DBL0255
Manufacturer	IDT
Description	PCIe Gen1-5 Clock Fanout Buffers
Published	May 23, 2020
Detailed Description	2 and 4-Output 3.3V PCIe Gen1–5 Clock Fanout Buffers with LOS 9DBL0255/9DBL0455 Datasheet Description The 9DBL0255/9DB...
Datasheet	9DBL0255 PDF File

Overview

2 and 4-Output 3.
3V PCIe Gen1–5 Clock Fanout Buffers with LOS 9DBL0255/9DBL0455 Datasheet Description The 9DBL0255/9DBL0455 are 2 and 4-output PCIe clock fanout buffers for PCIe Gen1–5 applications.
Both parts have a open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock.
The devices implement several additional features to aid robust designs.
Flexible Power Sequencing (FPS) ensures well-defined behavior under various power up scenarios, while Power Down Tolerant (PDT) ESD protection on all input pins allows input pins to be driven before VDD is applied.
The 9DBL0255 and 9DBL0455 are spread spectrum compatible and provides direct connection to 85Ω transmission lines.
They can also be used in 100Ω environments with simple external series resistors.
PCIe Architectures ▪ Common Clocked (CC) ▪ Independent Reference Clock (SRIS, SRnS) Typical Applications ▪ PCIe clock distribution in: • PCIe Riser Cards • NVME eSSD and JBOD • High-Performance Computing and Accelerators • Servers • Ethernet Switches Features ▪ 85Ω transmission lines require 0 termination resistors ▪ 100Ω transmission lines require only 2 series resistors per output ▪ OE# pin for each output supports PCIe CLKREQ# applications ▪ Intelligent power-down mode when all OE# pins are high (all outputs off) ▪ Industrial temperature range (-40°C to +85°C) ▪ Spread-spectrum tolerant ▪ Space saving 3 × 3 mm 16-VFQFPN (9DBL0255) ▪ Space saving 4 × 4 mm 20-VFQFPN (9DBL0455) ▪ Easy upgrade from 9DBL411B (9DBL0455) Key Features ▪ FPS: Input clock is internally biased so a floating input clock will not inject noise into system ▪ FPS: Open drain LOS# output indicates a loss of the input clock and returns the outputs to a Low/Low state ▪ PDT: Control inputs will not clamp to ground or VDD if a signal is applied before chip VDD is applied ▪ 2 or 4 Low-power HCSL (LP-HCSL) DIF pairs with 85Ω differential output impedance ▪ Easy AC-coupling to other logic families.
See IDT application n...

Similar Datasheet

9DBL02 2-output 3.3V PCIe Zero-Delay Buffer - IDT
9DBL0242 Zero-Delay/Fanout Buffer - Renesas
9DBL0242 2-output 3.3V PCIe Zero-Delay Buffer - IDT
9DBL0242C 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers - Renesas
9DBL0243 2-Output 3.3V LP-HCSL Zero-Delay Buffer - IDT
9DBL0252 Zero-Delay/Fanout Buffer - Renesas
9DBL0252 2-output 3.3V PCIe Zero-Delay Buffer - IDT
9DBL0252C 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers - Renesas
9DBL0253 2-Output 3.3V LP-HCSL Zero-Delay Buffer - IDT
9DBL0255 2 and 4-Output 3.3V PCIe Gen1-5 Clock Fanout Buffers - Renesas

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)