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70V26S

Renesas
Part Number 70V26S
Manufacturer Renesas
Description DUAL-PORT STATIC RAM
Published May 23, 2020
Detailed Description HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM 70V26S/L Features ◆ True Dual-Ported memory cells which allow simultaneo...
Datasheet PDF File 70V26S PDF File

70V26S
70V26S

Overview
HIGH-SPEED 3.
3V 16K x 16 DUAL-PORT STATIC RAM 70V26S/L Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Commercial: 25/35/55ns (max.
) ◆ Low-power operation – IDT70V26S Active: 300mW (typ.
) Standby: 3.
3mW (typ.
) – IDT70V26L Active: 300mW (typ.
) Standby: 660μW (typ.
) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT70V26 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ TTL-compatible, single 3.
3V (±0.
3V) power supply ◆ Available in 84-pin PGA and PLCC ◆ Green parts available, see ordering information Functional Block Diagram R/WL UBL R/WR UBR LBL CEL OEL I/O8L-I/O15L I/O0L-I/O7L BUSYL(1,2) A13L A0L I/O Control I/O Control Address Decoder 14 CEL MEMORY ARRAY ARBITRATION SEMAPHORE LOGIC Address Decoder 14 CER SEML NOTES: 1.
(MASTER): BUSY is output; (SLAVE): BUSY is input.
2.
BUSY outputs are non-tri-stated push-pull.
M/S ©2019 Integrated Device Technology, Inc.
1 LBR CER OER I/O8R-I/O15R I/O0R-I/O7R BUSYR(1,2) A13R A0R SEMR 2945 drw 01 JULY 2019 DSC 2945/19 70V26S/L High-Speed 16K x 16 Dual-Port Static RAM Description The IDT70V26 is a high-speed 16K x 16 Dual-Port Static RAM.
The IDT70V26 is designed to be used as a stand-alone 256K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-ormore word systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for Indust...


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