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54LS92

Motorola
Part Number 54LS92
Manufacturer Motorola
Description DECADE COUNTER
Published Aug 22, 2020
Detailed Description DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are h...
Datasheet PDF File 54LS92 PDF File

54LS92
54LS92

Overview
DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed 4-bit ripple type counters partitioned into two sections.
Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs.
Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters.
All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).
• Low Power Consumption .
.
.
Typically 45 mW • High Count Rates .
.
.
Typically 42 MHz • Choice of Counting Modes .
.
.
BCD, Bi-Quinary, Divide-by-Twelve, Binary • Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES LOADING (Note a) HIGH LOW CP0 CP1 CP1 MR1, MR2 MS1, MS2 Q0 Q1, Q2, Q3 Clock (Active LOW going edge) Input to ÷2 Section Clock (Active LOW going edge) Input to ÷5 Section (LS90), ÷6 Section (LS92) Clock (Active LOW going edge) Input to ÷8 Section (LS93) Master Reset (Clear) Inputs Master Set (Preset-9, LS90) Inputs Output from ÷2 Section (Notes b & c) Outputs from ÷5 (LS90), ÷6 (LS92), ÷8 (LS93) Sections (Note b) 0.
5 U.
L.
1.
5 U.
L.
0.
5 U.
L.
2.
0 U.
L.
0.
5 U.
L.
1.
0 U.
L.
0.
5 U.
L.
0.
5 U.
L.
10 U.
L.
10 U.
L.
0.
25 U.
L.
0.
25 U.
L.
5 (2.
5) U.
L.
5 (2.
5) U.
L.
NOTES: a.
1 TTL Unit Load (U.
L.
) = 40 µA HIGH/1.
6 mA LOW.
b.
The Output LOW drive factor is 2.
5 U.
L.
for Military, (54) and 5 U.
L.
for commercial (74) b.
Temperature Ranges.
c.
The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d.
To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
LS90 67 12 MS 14 CP0 1 CP1 MR Q0 Q1 Q2 Q3 12 2 3 12 9 8 11 VCC = PIN 5 GND = PIN 10 NC = PINS 4, 13 LOGIC SYMBOL LS92 14 CP0 1 CP1 MR Q0 Q1 Q2 Q3 12 6 7 12 11 9 8 VCC = PIN 5 GND = PIN 10 NC = PINS ...


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