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74V1G77

STMicroelectronics
Part Number 74V1G77
Manufacturer STMicroelectronics
Description SINGLE D-TYPE LATCH
Published Feb 28, 2021
Detailed Description 74V1G77 SINGLE D-TYPE LATCH s HIGH SPEED: tPD = 4.4ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 1µA(MAX.) at...
Datasheet PDF File 74V1G77 PDF File

74V1G77
74V1G77

Overview
74V1G77 SINGLE D-TYPE LATCH s HIGH SPEED: tPD = 4.
4ns (TYP.
) at VCC = 5V s LOW POWER DISSIPATION: ICC = 1µA(MAX.
) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.
) ) s POWER DOWN PROTECTION ON INPUTS t(s s SYMMETRICAL OUTPUT IMPEDANCE: c |IOH| = IOL = 8mA (MIN) at VCC = 4.
5V u s BALANCED PROPAGATION DELAYS: d tPLH ≅ tPHL ro s OPERATING VOLTAGE RANGE: P VCC(OPR) = 2V to 5.
5V s IMPROVED LATCH-UP IMMUNITY lete DESCRIPTION o The 74V1G77 is an advanced high-speed CMOS bs SINGLE D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal O wiring C2MOS technology.
It is designed to - operate from 2V to 5.
5V, making this device ideal t(s) for portable applications.
The single D-Type latch is controlled by a Latch c Enable Input (LE).
u While the LE input is held at a high level, the Q d output will follow the data input precisely.
When SOT23-5L SOT323-5L ORDER CODES PACKAGE SOT23-5L SOT323-5L T&R 74V1G77STR 74V1G77CTR the LE input is taken low the Q output is latched precisely at the logic level of D input data.
Power down protection is provided on inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.
This device can be used to interface 5V to 3V.
It’s available in the commercial and extended temperature range.
All inputs and output are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage.
Obsolete Pro PIN CONNECTION AND IEC LOGIC SYMBOLS April 2004 1/10 74V1G77 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN N° 1 2 4 3 5 SYMBOL D LE Q GND VCC NAME QND FUNCTION Data Input Latch Enable Input Data Output Ground (0V) Positive Supply Voltage TRUTH TABLE D LE Q L L No Change * t(s) H L No Change * L H Qn c H H Qn du (*) Q output is latched at the time when the le input is taken low logic level.
Pro ABSOLUTE MAXIMUM RATINGS te Symbol Parameter Value Unit ole VCC Supply Voltage -0.
5 to +7.
0 V s VI DC Input Voltage -0.
5...


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