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AD5313

Analog Devices
Part Number AD5313
Manufacturer Analog Devices
Description +2.5 V to +5.5 V/ 230 uA/ Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs
Published Mar 23, 2005
Detailed Description a +2.5 V to +5.5 V, 230 ␮A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs AD5303/AD5313/AD5323* GENERAL DESCRIPTI...
Datasheet PDF File AD5313 PDF File

AD5313
AD5313

Overview
a +2.
5 V to +5.
5 V, 230 ␮A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs AD5303/AD5313/AD5323* GENERAL DESCRIPTION FEATURES AD5303: Two Buffered 8-Bit DACs in One Package AD5313: Two Buffered 10-Bit DACs in One Package AD5323: Two Buffered 12-Bit DACs in One Package 16-Lead TSSOP Package Micropower Operation: 300 ␮ A @ 5 V (Including Reference Current) Power-Down to 200 nA @ 5 V, 50 nA @ 3 V +2.
5 V to +5.
5 V Power Supply Double-Buffered Input Logic Guaranteed Monotonic By Design Over All Codes Buffered/Unbuffered Reference Input Options Output Range: 0–VREF or 0–2 V REF Power-On-Reset to Zero Volts SDO Daisy-Chaining Option Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility Low Power Serial Interface with Schmitt-Triggered Inputs On-Chip Rail-to-Rail Output Buffer Amplifiers APPLICATIONS Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators The AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bit buffered voltage output DACs in a 16-lead TSSOP package that operate from a single +2.
5 V to +5.
5 V supply consuming 230 µA at 3 V.
Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.
7 V/µs.
The AD5303/ AD5313/AD5323 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI™, QSPI, MICROWIRE™ and DSP interface standards.
The references for the two DACs are derived from two reference pins (one per DAC).
These reference inputs may be configured as buffered or unbuffered inputs.
The parts incorporate a poweron-reset circuit that ensures that the DAC outputs power-up to 0 V and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears both DACs to 0 V.
The outputs of both DACs may be updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the curr...


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