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SN74AC10 Datasheet PDF

Texas Instruments
Part Number SN74AC10
Manufacturer Texas Instruments
Title Triple 3-Input Positive-NAND Gates
Description ordering information NC − No internal connection The ’AC10 devices contain three independent 3-input NAND gates. The devices perform the Boolean...
Features 0DBR AC10 AC10 TSSOP − PW Tube Tape and reel SN74AC10PW SN74AC10PWR AC10 CDIP − J Tube SNJ54AC10J SNJ54AC10J −55°C to 125°C CFP − W Tube SNJ54AC10W SNJ54AC10W LCCC − FK Tube SNJ54AC10FK SNJ54AC10FK † Package drawings, standard packing quantities, thermal data, symbolization, and PC...

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SN74AC10 SN74AC10 SN74AC10




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SN74ABT125 : ordering information NC − No internal connection The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup res.

SN74ABT125Q-Q1 : ordering information The SN74ABT125Q-Q1 quadruple bus buffer gate features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of th.

SN74ABT126 : ordering information NC − No internal connection The ’ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING QFN − RGY Tape and reel SN74ABT126RGYR AB126 −40°C to 85°C PDIP − N SOIC − D SOP − NS SSOP .

SN74ABT162244 : ordering information The ’ABT162244 devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide noninverting outputs and symmetrical active-low output-enable (OE) inputs. SN54ABT162244 WD PACKAGE SN74ABT162244 DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y2 20 GND 21 4Y3 22 4Y4 23 4OE 24 48 2OE 47 1A1 46 1A2 45 .

SN74ABT162245 : ordering information The ’ABT162245 devices are 16-bit noninverting 3-state transceivers designed for synchronous 2B4 17 VCC 18 2B5 19 2B6 20 32 2A4 31 VCC 30 2A5 29 2A6 two-way communication between data buses. GND 21 28 GND The control-function implementation minimizes 2B7 22 27 2A7 external timing requirements. 2B8 23 26 2A8 These devices can be used as two 8-bit 2DIR 24 25 2OE transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated..

SN74ABT16240A : The ’ABT16240A devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998 SN54ABT16240A WD PACKAGE SN74ABT16240A DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y2 20 GND 21 4Y3 22 4Y4 23 4OE 24 48 2OE 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC 41 2A1 40 2A2 39 GND 38 2A3 37 2A4 36 3A1 35 3A2 34 GND 33 3A3.

SN74ABT16241A : The ’ABT16241A devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. SN54ABT16241A, SN74ABT16241A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS096G – FEBRUARY 1991 – REVISED OCTOBER 1998 SN54ABT16241A WD PACKAGE SN74ABT16241A DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y2 20 GND 21 4Y3 22 4Y4 23 4OE 24 48 2OE 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC 41 2A1 40 2A2 39 GND 38 2A3 37 2A4 36 3A1 35 3A2 34 GND 33 3A3.

SN74ABT16244A : The SN54ABT16244 and SN74ABT16244A are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical OE (active-low output-enable) inputs. SN54ABT16244, SN74ABT16244A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS073H – SEPTEMBER 1991 – REVISED AUGUST 2005 SN54ABT16244 WD PACKAGE SN74ABT16244A DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13.

SN74ABT16245A : The 'ABT16245A devices are 16-bit noninverting 3-state transceivers designed for synchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. These devices can be used as two 8-bit transceviers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impendance st.

SN74ABT16245A-EP : ORDERING INFORMATION The SN74ABT16245A-EP is a 16-bit noninverting 3-state transceiver designed for synchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the hi.

SN74ABT162500 : .

SN74ABT162601 : These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. SN54ABT162601 WD PACKAGE SN74ABT162601 DGG OR DL PACKAGE (TOP VIEW) OEAB 1 LEAB 2 A1 3 GND 4 A2 5 A3 6 VCC 7 A4 8 A5 9 A6 10 GND 11 A7 12 A8 13 A9 14 A10 15 A11 16 A12 17 GND 18 A13 19 A14 20 A15 21 VCC 22 A16 23 A17 24 GND 25 A18 26 OEBA 27 LEBA 28 56 CLKENAB 55 CLKAB 54 B1 53 GND 52 B2 51 B3 50 VCC 49 B4 48 B5 47 .

SN74ABT162823A : ordering information These 18-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ’ABT162823A devices can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock. SN54ABT162823A, .

SN74ABT162827A : ordering information The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1 and 1OE2, or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. SN54ABT162827A, SN74ABT162827A 20ĆBIT BUFFERS/DRIVERS WITH 3ĆSTATE OUTPUTS SCBS248F − JULY 1993 − REVISED JUNE 2004 SN54ABT162827A WD PACKAGE SN74ABT1.

SN74ABT162841 : ordering information These 20-bit transparent D-type latches feature noninverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ’ABT162841 devices can be used as two 10-bit latches or one 20-bit latch. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. SN54ABT162841, SN74ABT162841 20ĆBIT BUSĆINTERFACE DĆTYPE LATCHES WITH 3ĆSTATE OUTPUTS SCBS665C −.

SN74ABT16373A : The ’ABT16373A are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54ABT16373A WD PACKAGE SN74ABT16373A DGG OR DL PACKAGE (TOP VIEW) 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2OE 24 48 1LE 47 1D1 46 1D2 45 GND 44 1D3 43 1D4 42 VCC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 36 2D1 35 2D2 34 GND 33 2D3 32 2D4 31 VCC 30 2D5 29 2D6 28 GND 27 2D7 26 2D8 25 2LE T.

SN74ABT16373A-EP : ORDERING INFORMATION The SN74ABT16373A-EP is a 16-bit transparent D-type latch with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The SN74ABT16373A-EP is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. TA –55°C to 125°C SSOP – DL ORDERING INFORMATION PACKAGE (1) ORDERABLE PART NUMBER Tape and reel CABT16373AMDLREP TOP-SIDE MARKING ABT16373AMEP (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, stand.




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