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DM74ALS137

Fairchild Semiconductor
Part Number DM74ALS137
Manufacturer Fairchild Semiconductor
Description 3 to 8 Line Decoder/Demultiplexer with Address Latches
Published Apr 1, 2005
Detailed Description DM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches February 1991 Revised February 2000 DM74ALS137 3 to ...
Datasheet PDF File DM74ALS137 PDF File

DM74ALS137
DM74ALS137

Overview
DM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches February 1991 Revised February 2000 DM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches General Description The ALS137 is a three line to eight line decoder/demultiplexer with latches on the three address inputs.
When the latch-enable input (GL) is LOW, the ALS137 acts as a decoder/demultiplexer.
When GL goes from LOW-to-HIGH, the address present at the select inputs (A, B, and C) is stored in the latches.
Further address changes are ignored as long as GL remains HIGH.
The output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.
All of the outputs are HIGH unless G1 is HIGH and G2 is LOW.
The ALS137 is ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.
Features s Combines decoder and 3-bit address latch s Incorporates 3 enable inputs to simplify cascading s Low power dissipation: 28 mW typ s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process Ordering Code: Order Number DM74ALS137M DM74ALS137N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.
150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.
300 Wide Devices also available in Tape and Reel.
Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table Inputs Enable GL G1 G2 C X X L L L L L L L L H X L H H H H H H H H H H X L L L L L L L L L X X L L L L H H H H X Select B X X L L H H L L H H X Outputs A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L H L H L H L H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L X Output corresponding to stored address, L; all others, H L = LOW State H = HIGH State X = Don't Care...


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