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74AHC1G14

NXP
Part Number 74AHC1G14
Manufacturer NXP
Description Inverting Schmitt trigger
Published Apr 3, 2005
Detailed Description 74AHC1G14; 74AHCT1G14 Inverting Schmitt trigger Rev. 7 — 18 November 2014 Product data sheet 1. General description ...
Datasheet PDF File 74AHC1G14 PDF File

74AHC1G14
74AHC1G14

Overview
74AHC1G14; 74AHCT1G14 Inverting Schmitt trigger Rev.
7 — 18 November 2014 Product data sheet 1.
General description 74AHC1G14 and 74AHCT1G14 are high-speed Si-gate CMOS devices.
They provide an inverting buffer function with Schmitt trigger action.
These devices are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.
5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.
5 V to 5.
5 V.
2.
Features and benefits  Symmetrical output impedance  High noise immunity  ESD protection:  HBM JESD22-A114E: exceeds 2000 V  MM JESD22-A115-A: exceeds 200 V  CDM JESD22-C101C: exceeds 1000 V  Low power dissipation  Balanced propagation delays  SOT353-1 and SOT753 package options  Specified from 40 C to +125 C 3.
Applications  Wave and pulse shapers  Astable multivibrators  Monostable multivibrators 4.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name 74AHC1G14GW 40 C to +125 C TSSOP5 74AHCT1G14GW 74AHC1G14GV 40 C to +125 C SC-74A 74AHCT1G14GV Description plastic thin shrink small outline package; 5 leads; body width 1.
25 mm plastic surface-mounted package; 5 leads Version SOT353-1 SOT753 NXP Semiconductors 74AHC1G14; 74AHCT1G14 Inverting Schmitt trigger 5.
Marking Table 2.
Marking codes Type number 74AHC1G14GW 74AHCT1G14GW 74AHC1G14GV 74AHCT1G14GV Marking code[1] AF CF A14 C14 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6.
Functional diagram $ < PQD Fig 1.
Logic symbol  PQD Fig 2.
IEC logic symbol 7.
Pinning information 7.
1 Pinning $+&* $+&7* QF   9&& $ Fig 4.
Pin configuration *1'  < DDI 7.
2 Pin description Table 3.
Symbol n.
c.
A GND Y VCC Pin description Pin 1 2 3 4 5 Description not connected data input ground (0 V) data output suppl...


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