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74AHCT374

NXP
Part Number 74AHCT374
Manufacturer NXP
Description Octal D-type flip-flop
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET 74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state Product spec...
Datasheet PDF File 74AHCT374 PDF File

74AHCT374
74AHCT374

Overview
INTEGRATED CIRCUITS DATA SHEET 74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state Product specification Supersedes data of 1998 Dec 11 File under Integrated Circuits, IC06 1999 Sep 28 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accepts voltages higher than VCC • Common 3-state output enable input • ICC category: MSI • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.
0 ns.
DESCRIPTION 74AHC374; 74AHCT374 The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard No.
7A.
The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops.
The ‘374’ is functionally identical to the ‘534’, but has non-inverting outputs.
TYPICAL SYMBOL tPHL/tPLH fmax CI CO CPD Notes 1.
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = sup...


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