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74F112

NXP
Part Number 74F112
Manufacturer NXP
Description Dual J-K negative edge-triggered flip-flop
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74F112 Dual J-K negative edge-triggered flip-flop Product specification IC15 Data Handbook 1990 Feb...
Datasheet PDF File 74F112 PDF File

74F112
74F112

Overview
INTEGRATED CIRCUITS 74F112 Dual J-K negative edge-triggered flip-flop Product specification IC15 Data Handbook 1990 Feb 09 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74F112 FEATURE • Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and data will be accepted.
The logic levels at the J and K inputs may be allowed to change while the CPn is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed.
Output changes are initiated by the High-to-Low transition of the CPn.
TYPE ...


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