DatasheetsPDF.com

74F114

Part Number	74F114
Manufacturer	Fairchild Semiconductor
Description	Dual JK Negative Edge-Triggered Flip-Flop
Published	Apr 3, 2005
Detailed Description	74F114 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised August 1999 74F114 Dual JK Negative Edge-Triggered...
Datasheet	74F114 PDF File

Overview

74F114 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs.
Synchronous state changes are initiated by the falling edge of the clock.
Triggering occurs at a voltage level of the clock and is not directly related to the transition time.
The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock.
A LOW signal on SD or CD preve...

Similar Datasheet

74F10 Triple 3-input NAND gate - NXP
74F10 Triple 3-Input NAND Gate - Fairchild Semiconductor
74F10 Triple 3-Input NAND Gate - National Semiconductor
74F10 TRIPLE 3-INPUT POSITIVE-NAND GATE - Texas Instruments
74F1056 8-Bit Schottky Barrier Diode Array - Fairchild Semiconductor
74F1071 18-Bit Undershoot/Overshoot Clamp - Fairchild Semiconductor
74F109 Dual JK Positive Edge-Triggered Flip-Flop - National Semiconductor
74F109 Positive J-K positive edge-triggered flip-flops - NXP
74F109 Dual JK Positive Edge-Triggered Flip-Flop - Fairchild Semiconductor
74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP - Texas Instruments

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)