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ISP1181

NXP
Part Number ISP1181
Manufacturer NXP
Description Full-speed Universal Serial Bus interface device
Published Apr 5, 2005
Detailed Description ISP1181 Full-speed Universal Serial Bus interface device Rev. 01 — 13 March 2000 Objective specification 1. General desc...
Datasheet PDF File ISP1181 PDF File

ISP1181
ISP1181

Overview
ISP1181 Full-speed Universal Serial Bus interface device Rev.
01 — 13 March 2000 Objective specification 1.
General description The ISP1181 is a Universal Serial Bus (USB) interface device which complies with Universal Serial Bus Specification Rev.
1.
1.
It provides full-speed USB communication capacity to microcontroller or microprocessor-based systems.
The ISP1181 communicates with the system’s microcontroller or microprocessor through a high-speed general-purpose parallel interface.
The fully autonomous Direct Memory Access (DMA) operation - auto download, auto repeat, auto execution - removes the need for the device to re-enable or re-initialize the DMA operation every time.
The modular approach to implementing a USB interface device allows the designer to select the optimum system microcontroller from the wide variety available.
The ability to re-use existing architecture and firmware investments shortens development time, eliminates risks and reduces costs.
The result is fast and efficient development of the most cost-effective USB peripheral solution.
The ISP1181 is ideally suited for application in many personal computer peripherals, such as printers, scanners, external mass storage (zip drive) devices and digital still cameras.
It offers an immediate cost reduction for applications that currently use SCSI implementations.
c c 2.
Features s Complies with Universal Serial Bus Specification Rev.
1.
1 and most Device Class specifications s High performance USB interface device with integrated Serial Interface Engine (SIE), FIFO memory, transceiver and 3.
3 V voltage regulator s Interrupt endpoint can be configured in ‘rate feedback’ mode s High speed (11.
1 Mbyte/s or 90 ns read/write cycle) parallel interface s Fully autonomous and multi-configuration DMA operation s Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints s Integrated physical 2462 bytes of multi-configuration FIFO memory s Endpoints with double buffering to increase throughput and ease...


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