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UPD16664

NEC
Part Number UPD16664
Manufacturer NEC
Description 144/160/184/208-OUTPUT LCD COLUMN SEGMENT DRIVER
Published Apr 17, 2005
Detailed Description DATA SHEET MOS INTEGRATED CIRCUIT µ PD16664 144/160/184/208-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH RAM DESCRIPTION T...
Datasheet PDF File UPD16664 PDF File

UPD16664
UPD16664

Overview
DATA SHEET MOS INTEGRATED CIRCUIT µ PD16664 144/160/184/208-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH RAM DESCRIPTION The µ PD16664 is a column (segment) driver with internal RAM and can drive a full-dot LCD.
Equipped with 144/160/184/208-output pins and a display RAM of 208 x 160 x 2 bits, this driver can display any of four gray levels selected from a 25-level palette.
By using this IC in combination with the µ PD16667, 144 x 128 pixels to 416 x 320 pixels can be displayed.
FEATURES • Internal display RAM : 208 x 160 x 2 bits • Logic voltage • Duty • Number of outputs • Display : 2.
4 to 3.
6 V : 1/128, 1/160 selectable : 144,160,184 and 208 pins selectable : Four gray levels (selectable from 25-level palette) • Memory management : Packed pixel method • Supports 8/16-bit data bus ORDERING INFORMATION Part number Package TCP (TAB) 2/4-side Standard TCP µ PD16664N-xxx µ PD16664N-001 Remark The TCP’s external shape is customized.
To order the required shape, please contact an NEC salesperson.
The information in this document is subject to change without notice.
Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country.
Please check with local NEC representative for availability and additional information.
Document No.
S13780EJ1V0DS00(1st edition) Date Published September 1999 NS CP(K) Printed in Japan The mark • shows major revised points.
© 1998, 1999 µ PD16664 1.
PIN NAME Pin NameNote D0-D15 A0-A16 /CS VCC2 /OE /WE /UBE RDY Control signals PL0 PL1 DIR DMODE CMODE0,1 MS VCC2 BMODE /REFRH TEST /RESET /DOFF OSC1 OSC2 STB /FRM VCC1 PULSE L1 L2 /DOUT Liquid crystal drive Power Y1-Y208 GND VCC1 VCC2 V0 V1 V2 Classification CPU interface I/O I/O I I I I I O I I I I I I I I/O I I I – – I/O I/O I/O I/O I/O O O – – – – – – Data bus: 16 bits Address bus: 17 bits Chip select Read signal Write signal Upper byte enable Function Ready signal to CPU (“H”: ready) Specifies LSI layout position (No.
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