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74HCT251

Philips
Part Number 74HCT251
Manufacturer Philips
Description 8-input multiplexer
Published Apr 23, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Fam...
Datasheet PDF File 74HCT251 PDF File

74HCT251
74HCT251

Overview
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT251 8-input multiplexer; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-input multiplexer; 3-state FEATURES • True and complement outputs • Both outputs are 3-state for further multiplexer expansion • Multifunction capability • Permits multiplexing from n-lines to one line • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT251 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no.
7A.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT251 The 74HC/HCT251 are the logic implementations of single-pole 8-position switches with the state of three select inputs (S0, S1, S2) controlling the switch positions.
Assertion (Y) and negation (Y) outputs are both provided.
The output enable input (OE) is active LOW.
The logic function provided at the output, when activated, is: Y = OE.
(I0.
S0.
S1.
S2 + I1.
S0.
S1.
S2 + + I2.
S0.
S1.
S2 + I3.
S0.
S1.
S2 + + I4.
S0.
S1.
S2 + I5.
S0.
S1.
S2 + + I6.
S0.
S1.
S2 + I7.
S0.
S1.
S2) Both outputs are in the high impedance OFF-state (Z) when the output enable input is HIGH, allowing multiplexer expansion by tying the outputs.
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay In to Y In to Y Sn to Y Sn to Y CI CPD Notes 1.
CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2.
For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.
5 V ORDER...


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