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74LS48

Motorola
Part Number 74LS48
Manufacturer Motorola
Description BCD TO 7-SEGMENT DECODER
Published Apr 23, 2005
Detailed Description SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buf...
Datasheet PDF File 74LS48 PDF File

74LS48
74LS48

Overview
SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates.
Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates.
The remaining NAND gate and three input buffers provide lamp test, blanking input/rippleblanking input for the LS48.
The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on the state of the auxiliary inputs, decodes this data to drive other components.
The relative positive logic output levels, as well as conditions required at the auxiliary inputs, are shown in the truth tables.
The LS48 circuit incorporates automatic leading and / or trailing edge zero-blanking control (RBI and RBO).
Lamp Test (LT) may be activated any time when the BI / RBO node is HIGH.
Both devices contain an overriding blanking input (BI) which can be used to control the lamp intensity by varying the fre...


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