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74LS73

Part Number	74LS73
Manufacturer	Motorola
Description	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Published	Apr 23, 2005
Detailed Description	SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inp...
Datasheet	74LS73 PDF File

Overview

SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs.
These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted.
The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed.
Input data is transferred to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q 13 (8) Q 12 (9) 1 CLEAR 2 (6) K 3 (10)...

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