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MC100LVEL51

ON Semiconductor
Part Number MC100LVEL51
Manufacturer ON Semiconductor
Description Differential Clock D Flip-Flop
Published Apr 26, 2005
Detailed Description 3.3 V ECL Differential Clock D Flip‐Flop MC100LVEL51 Description The MC100LVEL51 is a differential clock D flip-flop wi...
Datasheet PDF File MC100LVEL51 PDF File

MC100LVEL51
MC100LVEL51

Overview
3.
3 V ECL Differential Clock D Flip‐Flop MC100LVEL51 Description The MC100LVEL51 is a differential clock D flip-flop with reset.
The device is functionally equivalent to the EL51 device, but operates from a 3.
3 V supply.
With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.
3 V VCC.
The reset input is an asynchronous, level triggered signal.
Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.
The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under open input conditions.
When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2.
Features • 475 ps Propagation Delay • 2.
8 GHz Toggle Frequency • ESD Protection: > 4 kV Human Body Model, > 200 V Machine Model • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range: VCC = 3.
0 V to 3.
8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.
0 V to −3.
8 V • Internal Input Pulldown Resistors • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level ♦ Level 1 for SOIC−8 NB ♦ Level 3 for TSSOP−8 ♦ For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.
125 in, Oxygen Index: 28 to 34 • Transistor Count = 114 devices • These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.
onsemi.
com 8 1 SOIC−8 NB D SUFFIX CASE 751 8 1 TSSOP−8 DT SUFFIX CASE 948R MARKING DIAGRAMS* 8 KVL51 ALYW G 1 SOIC−8 8 KV51 ALYWG G 1 TSSOP−8 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8...


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