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MC14027B

ON Semiconductor
Part Number MC14027B
Manufacturer ON Semiconductor
Description Dual J-K Flip-Flop
Published Apr 26, 2005
Detailed Description MC14027B Dual J-K Flip-Flop The MC14027B dual J−K flip−flop has independent J, K, Clock (C), Set (S) and Reset (R) inp...
Datasheet PDF File MC14027B PDF File

MC14027B
MC14027B

Overview
MC14027B Dual J-K Flip-Flop The MC14027B dual J−K flip−flop has independent J, K, Clock (C), Set (S) and Reset (R) inputs for each flip−flop.
These devices may be used in control, register, or toggle functions.
Features • Diode Protection on All Inputs • Supply Voltage Range = 3.
0 Vdc to 18 Vdc • Logic Swing Independent of Fanout • Logic Edge−Clocked Flip−Flop Design • Logic State is Retained Indefinitely with Clock Level Either High or Low; Information is Transferred to the Output Only on the Positive−Going Edge of the Clock Pulse • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Pin−for−Pin Replacement for CD4027B • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD Vin, Vout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) −0.
5 to +18.
0 −0.
5 to VDD + 0.
5 V V Iin, Iout Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device.
If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1.
Temperature Derating: “D/DW” Packages: –7.
0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit.
For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused...


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