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74LVQ14 Datasheet PDF

Fairchild Semiconductor
Part Number 74LVQ14
Manufacturer Fairchild Semiconductor
Title Low Voltage Hex Inverter
Description The LVQ14 contains six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharp...
Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number 74LVQ14SC 74LVQ14SJ Package Number M14A M14D Pack...

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74LVQ14 74LVQ14 74LVQ14




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74LVQ00 : The LVQ00 is a low voltage CMOS QUAD 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/8 74LVQ00 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCT ION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L L H H B L H L H Y H H H L ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) P.

74LVQ00 : The LVQ00 contains four 2-input NAND gates. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number 74LVQ00SC 74LVQ00SJ See Package Description 14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC 14-Lead Small Outline Package, SOIC EIAJ Package Number M14A M14D Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Assignment for for SOIC JEDEC and EIAJ DS011341-1 DS01.

74LVQ02 : The LVQ02 is a low voltage CMOS QUAD 2-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/8 74LVQ02 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 2, 5, 8, 11 3, 6, 9, 12 1, 4, 10, 13 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCT ION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L L H H B L H L H Y H L L L ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Pa.

74LVQ02 : The LVQ02 contains four 2-input NOR gates. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number 74LVQ02SC 74LVQ02SJ Package Number M14A M14D Package Description 14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC 14-Lead Small Outline Package, SOIC EIAJ Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Assignment for SOIC JEDEC and EIAJ DS011342-1 DS011342-2 Pin.

74LVQ04 : The LVQ04 is a low voltage CMOS HEX INVERTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/8 74LVQ04 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 5, 9, 11, 13 2, 4, 6, 8, 10, 12 7 14 SYMBOL 1A to 6A 1Y to 6Y GND VCC NAME AND FUNCT ION Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L H Y H L ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5.

74LVQ04 : The LVQ04 contains six inverters. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Ordering Number 74LVQ04SC 74LVQ04SJ Package Number M14A M14D Package Description 14-Lead (0.150" Wide) Molded Small Outline Package, SOIC JEDEC 14-Lead Molded Small Outline Package, SOIC EIAJ Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Assignment for SOIC JEDEC and EIAJ DS011343-1 DS011343-2 Pin Descript.

74LVQ08 : The LVQ08 is a low voltage CMOS QUAD 2-INPUT AND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/8 74LVQ08 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCT ION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L L H H B L H L H Y L L L H ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Pa.

74LVQ08 : The LVQ08 contains four, 2-input AND gates. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number 74LVQ08SC 74LVQ08SJ Package Number M14A M14D Package Description 14-Lead (0.150" Wide) Molded Small Outline Package, SOIC JEDEC 14-Lead Molded Small Outline Package, SOIC EIAJ Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Assignment for SOIC JEDEC and EIAJ DS011344-1 DS011344-2 Pin De.

74LVQ125 : The LVQ125 is a low voltage CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/8 74LVQ125 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYMBOL 1G to 4G 1A to 4A 1Y to 4Y GND VCC NAME AND FUNCT ION Output Enable Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A X L H X:”H” or ”L” Z: High Impedance G H L L Y Z L H ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Tempera.

74LVQ125 : The LVQ125 contains four independent non-inverting buffers with 3-STATE outputs. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number 74LVQ125SC 74LVQ125SJ Package Number M14A M14D Package Description 14-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC 14-Lead Small Outline Package, SOIC EIAJ Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Assignment for SOIC JEDEC and EIAJ.

74LVQ138 : The LVQ138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/9 74LVQ138 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 3 4, 5 6 15, 14, 13, 12, 11, 10, 9, 7 8 16 SYMBOL A, B, C G2A, G2B G1 Y0 to Y7 NAME AND FUNCT ION Address Inputs Enable Inputs Enable Input Outputs GND VCC Ground (0V) Positive Supply Voltage TRUTH TABLE INPUT S ENABL E G2B G2A G1 C X X L X X H X X H X X X L L H L L L H L L L H L L L H L L L H H L L H H L L H H L L H H X:Don’t Care OUTPUTS SELECT B .

74LVQ138 : The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LVQ138 devices or a 1-of-32 decoder using four LVQ138 devices and one inverter. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75Ω n 4 kV minimum ESD immunity n Demultiplexing capability n Multiple input enable for each expansion n Active LOW mutually exclusive outputs Ordering Code: Order Numbe.

74LVQ14 : The LVQ14 is a low voltage CMOS HEX SCHMITT INVERTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. The internal circuit is composed of 3 stages PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/8 74LVQ14 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 5, 9, 11, 13 2, 4, 6, 8, 10, 12 7 14 SYMBOL 1A to 6A 1Y to 6Y GND VCC NAME AND FUNCT ION Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L H Y H L ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Dio.

74LVQ151 : The LVQ151 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one line of data from up to eight sources. The LVQ151 can be used as a universal function generator to generate any logic function of four variables. Both true and complementary outputs are provided. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number 74LVQ151SC 74LVQ151SJ Package Number M16A M16D Package Description 16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDE.

74LVQ157 : The LVQ157 is a low voltage CMOS QUAD 2-CHANNEL MULTIPLEXER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. PIN CONNECTION AND IEC LOGIC SYMBOLS It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. It consists of four 2-input digital multiplexers with common select and strobe inputs. When strobe input is held high selection of data is inhibit and all the outputs become low. The SELECT decoding determines whether the A or B inputs get routed to their corresponding Y outputs. All inputs and outputs are equipped with protection circuits a.

74LVQ157 : The LVQ157 is a high-speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four outputs present the selected data in the true (noninverted) form. The LVQ157 can also be used as a function generator. Features n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω. Ordering Code: Order Number 74LVQ157SC 74LVQ157SJ Package Number M16A M16D Package Description 16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC 16-Lead Molded Small Outline .




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