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82C88


Part Number 82C88
Manufacturer Intersil Corporation
Title CMOS Bus Controller
Description The Intersil 82C88 is a high performance CMOS Bus Controller manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C...
Features
• Compatible with Bipolar 8288
• Performance Compatible with: - 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz) - 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8MHz) - 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz) - 8089
• Provi...

File Size 129.58KB
Datasheet 82C88 PDF File








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82C814 : .... 6 3.2.1 3.2.2 3.2.3 3.2.4 3.3 Host Interface PCI Signals ..... 6 Docking Control and Sense Signals ... 7 PCI Docking Interface Pins..... 7 Interrupt Interface Pins ..... 8 Strap-Selected Interfac.

82C82 : The Intersil 82C82 is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C82 provides an eight-bit parallel latch/buffer in a 20 pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this signal. The active low output enable (OE) permits simple interface to state-of-the-art microprocessor systems. Features • Full Eight-Bit Parallel Latching Buffer • Bipolar 8282 Compatible • Three-State Noninverting Outputs • Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max. • Gated Inputs: - Reduce Operating Power - Eliminate the Nee.

82C82 : The Intersil 82C82 is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C82 provides an eight-bit parallel latch/buffer in a 20 pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this signal. The active low output enable (OE) permits simple interface to state-of-the-art microprocessor systems. Pinouts 82C82 (PDIP, CERDIP) TOP VIEW 82C82 (PLCC, CLCC) TOP VIEW DI2 DI1 DI0 VCC DO0 DI0 1 DI1 2 DI2 3 DI3 4 DI4 5 DI5 6 DI6 7 DI7 8 OE 9 GND 10 20 VCC 19 DO0 18 DO1 17 DO2 16 DO3 15 DO4 14 DO5 13 DO6 12 DO7 11 STB 3 2 1 20 19 DI3 DI4 DI.

82C836 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 2-9 Section 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Backup and Power-Up/Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T.

82C83H : The Intersil 82C83H is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C83H provides an 8bit parallel latch/buffer in a 20 lead pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this signal. The active low output enable (OE) permits simple interface to microprocessor systems. The 82C83H provides inverted data at the outputs. Features • Full 8-Bit Parallel Latching Buffer • Bipolar 8283 Compatible • Three-State Inverting Outputs • Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max • Gated Inputs - Reduce Operati.

82C84A : The Intersil 82C84A is a high performance CMOS Clock Generatordriver which is designed to service the requirements of both CMOS and NMOS microprocessors such as the 80C86, 80C88, 8086 and the 8088. The chip contains a crystal controlled oscillator, a divide-bythree counter and complete “Ready” synchronization and reset logic. Static CMOS circuit design permits operation with an external frequency source from DC to 25MHz. Crystal controlled operation to 25MHz is guaranteed with the use of a parallel, fundamental mode crystal and two small load capacitors. All inputs (except X1 and RES) are TTL compatible over temperature and voltage ranges. Power consumption is a fraction of that of the equiv.

82C84A : SYMBOL NUMBER TYPE DESCRIPTION AEN1, AEN2 3, 7 I ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are useful in system configurations which permit the processor to access two Multi-Master System Busses. In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW). RDY1, RDY2 4, 6 I BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a device located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1 while RDY2 is qualified by AEN2. ASYNC 15 I READY SYNC.

82C85 : The Intersil 82C85 Static CMOS Clock Controller/Generator provides complete control of static CMOS system operating modes and supports full speed, slow, stop-clock and stop-oscillator operation. While directly compatible with the Intersil 80C86 and 80C88 16-bit Static CMOS Microprocessor Family, the 82C85 can also be used for general system clock control. For static system designs, separate signals are provided on the 82C85 for stop (S0, S1, S2/STOP) and start (START) control of the crystal oscillator and system clocks. A single control line (SLO/FST) determines 82C85 fast (crystal/EFI frequency divided by 3) or slow (crystal/EFI frequency divided by 768) mode operation. Automatic maximum mo.

82C862 : ....6 3.3.1 Clock and Reset Interface Signals .....6 3.3.2 PCI Bus Interface Signals.6 3.3.3 USB Interface Signals 8 3.3.4 Host Controller shared signals: PME#, SMI#, REQ#.

82C86H : The Intersil 82C86H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C86H provides a full eight-bit bi-directional bus interface in a 20 lead package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C86H has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation. Features • Full Eight Bit Bi-Directional Bus Interface • Industry Standard 8286 Compatible Pinout • High Drive Capability - B Side IOL . . . . . . . . . . . . . . . . .

82C86H : The Intersil 82C86H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C86H provides a full eight-bit bi-directional bus interface in a 20 lead package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C86H has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation. Ordering Information PART NUMBER 8MHz ID82C86H PACKAGE TEMP. RANGE PKG DWG. # 20 Ld CERDIP -40oC to +85oC F20.3 Pinout 82C86H (CERDIP) TOP VIEW A0 1 A1 2 A2 3 A3 .

82C87H : The Intersil 82C87H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C87H provides a full eight-bit bi-directional bus interface in a 20 pin package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C87H has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation. The 82C87H provides inverted data at the outputs. Features • Full Eight Bit Bi-Directional Bus Interface • Industry Standard 8287 Compatible Pinout • High Drive Capabil.

82C88 : PIN SYMBOL NUMBER TYPE DESCRIPTION VCC GND 20 10 VCC: The +5V power supply pin. A 0.1F capacitor between pins 10 and 20 is recommended for decoupling. GROUND. S0, S1, S2 19, 3, 18 I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The 82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins are not in use (passive), command outputs are held HIGH (See Table1). CLK 2 I CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock generator and serves to establish when command/control signals are generated. ALE 5 O ADDRESS LATCH ENABLE: This signal .

82C89 : The Intersil 82C89 Bus Arbiter is manufactured using a selfaligned silicon gate CMOS process (Scaled SAJI IV). This circuit, along with the 82C88 bus controller, provides full bus arbitration and control for multi-processor systems. The 82C89 is typically used in medium to large 80C86 or 80C88 systems where access to the bus by several processors must be coordinated. The 82C89 also provides high output current and capacitive drive to eliminate the need for additional bus buffering. Static CMOS circuit design insures low operating power. The advanced Intersil SAJI CMOS process results in performance equal to or greater than existing equivalent products at a significant power savings. Features.




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