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P4C198

Part Number	P4C198
Manufacturer	ETC
Description	ULTRA HIGH SPEED 16K x 4
Published	May 13, 2005
Detailed Description	P4C198/198L, P4C198A/198AL P4C198/P4C198L, P4C198A/P4C198AL ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS FEATURES Full CMO...
Datasheet	P4C198 PDF File

Overview

P4C198/198L, P4C198A/198AL P4C198/P4C198L, P4C198A/P4C198AL ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) Low Power Operation (Commercial/Military) – 715 mW Active – 12/15 – 550/660 mW Active – 20/25/35/45/55 – 193/220 mW Standby (TTL Input) – 83/110 mW Standby (CMOS Input) P4C198/198A – 9 mW Standby (CMOS Input) P4C198L/198AL (Military) 5V ± 10% Power Supply Data Retention, 10 µA Typical Current from 2.
0V P4C198L/198AL (Military) Output Enable & Chip Enable Control Functions – Single Chip Enable P4C198 – Dual Chip Enable P4C198A Common Inputs and Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOJ (P4C198 only) – 28-Pin 350 x 550 mil LCC (P4C198 only) DESCRIPTION The P4C198/L and P4C198A/L are 65,536-bit ultra highspeed static RAMs organized as 16K x 4.
Each device features an active low Output Enable control to eliminate data bus contention.
The P4C198/L also have an active low Chip Enable (the P4C198A/L have two Chip Enables, both active low) for easy system expansion.
The CMOS memories require no clocks or refreshing and have equal access and cycle times.
Inputs are fully TTL-compatible.
The RAMs operate from a single 5V ± 10% tolerance power supply.
Data integrity is maintained with supply voltages down to 2.
0V.
Current drain is typically 10 µA from a 2.
0V supply.
Access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715 mW active, 193 mW standby.
The P4C198/L and P4C198A/L are available in 24-pin 300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC packages providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM A (8) A I/O 1 I/O 2 I/O 3 I/O 4 INPUT DATA CONTROL COLUMN I/O ROW SELECT 65,536-BIT MEMORY ARRAY PIN CONFI...

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