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74F243 Datasheet PDF

Fairchild
Part Number 74F243
Manufacturer Fairchild
Title Quad Bus Transceiver
Description The 74F243 is a quad bus transmitter/receiver designed for 4-line asynchronous 2-way data communications between data busses. Features s 2-Way as...
Features s 2-Way asynchronous data bus communication s Input clamp diodes limit high-speed termination effects Ordering Code: Order Code 74F243SC Package Number M14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Devices also available in Tape and Reel. Spec...

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74F20 : These devices contain two independent 4-input NAND gates. They perform the Boolean functions Y = A • B • C • D or Y = A + B + C + D in positive logic. The SN54F20 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74F20 is characterized for operation from 0°C to 70°C. SDFS041A – MARCH 1987 – REVISED OCTOBER 1993 SN54F20 J PACKAGE SN74F20 D OR N PACKAGE (TOP VIEW) 1A 1 1B 2 NC 3 1C 4 1D 5 1Y 6 GND 7 14 VCC 13 2D 12 2C 11 NC 10 2B 9 2A 8 2Y SN54F20 FK PACKAGE (TOP VIEW) 2D VCC NC 1A 1B FUNCTION TABLE (each gate) INPUTS OUTPUT A B C D Y H H H H L L X X X H X L X X H X X L X H X X X L H lo.

74F20 : 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F20N N74F20D PKG DWG # SOT27-1 D0c D0d Q0 GND SF00065 SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Dna, Dnb, Dnc, Dnd Q0, Q1 Data inputs Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC DIAGRAM D0a D0b D0c D0d 1 2 6 4 5 Q0 FUNCTION TABLE INPUTS Dna L X X 9 10 8 12 13 Q1 OUTPUT Dnd X X X L H Qn H H H H L X X L X H Dnb X L X X Dnc X D1a D1b D1c VCC = Pin 14 GND = Pin 7 D1d H H NOTES: H = High voltage level L = Low voltage leve.

74F20 : This device contains two independent gates, each of which performs the logic NAND function. Ordering Code: Order Number 74F20SC 74F20SJ 74F20PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Unit Loading/Fan Out U.L. Pin Names An, Bn, Cn, Dn On Description HIGH/LOW Inputs Outputs 1.0/1.0 50/33.3 Input IIH/I IL Output I OH/IOL 20 µA/−0..

74F20 : This device contains two independent gates each of which performs the logic NAND function Commercial 74F20PC Military Package Number N14A Package Description 14-Lead (0 300 Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0 150 Wide) Molded Small Outline JEDEC 14-Lead (0 300 Wide) Molded Small Outline EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F20DM (Note 2) 74F20SC (Note 1) 74F20SJ (Note 1) 54F20FM (Note 2) 54F20LM (Note 2) J14A M14A M14D W14B E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbol IEEE IEC Connec.

74F219 : The 74F219 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are 3-STATE and are in the high-impedance state whenever the Chip Select (CS) input is HIGH. The outputs are active only in the Read mode. This device is similar to the 74F189 but features non-inverting, rather than inverting, data outputs. Features s 3-STATE outputs for data bus applications s Buffered inputs minimize loading s Address decoding on-chip s Diode clamped inputs minimize ringing s Available in SOIC (300 mil only) Ordering Code: Order Number 74F219SC 74F219SJ 74F219PC Package Number M16B M16D N16E Package Descrip.

74F219 : The ’F219 is a high-speed 64-bit RAM organized as a 16-word by 4-bit array Address inputs are buffered to minimize loading and are fully decoded on-chip The outputs are TRI-STATE and are in the high-impedance state whenever the Chip Select (CS) input is HIGH The outputs are active only in the Read mode This device is similar to the ’F189 but features non-inverting rather than inverting data outputs Features Y Y Y Y Y TRI-STATE outputs for data bus applications Buffered inputs minimize loading Address decoding on-chip Diode clamped inputs minimize ringing Available in SOIC (300 mil only) Commercial 74F219PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dua.

74F219A : The 74F219A is a high speed, 64–bit RAM organized as a 16–word by 4–bit array. Address inputs are buffered to minimize loading and are fully decoded on chip. The outputs are in high impedance state whenever the chip enable (CE) is high. The outputs are active only in the READ mode (WE = high) and the output data is the complement of the stored data. Q1 7 GND 8 SF00307 TYPE 74F219A TYPICAL ACCESS TIME 5.0ns TYPICAL SUPPLY CURRENT(TOTAL) 55mA ORDERING INFORMATION ORDER CODE DESCRIPTION 16-pin plastic Dual In-line Package 16-pin plastic Small Outline (150mil) 16-pin plastic Small Outline Large (300mil) COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F219AN N74F219AD C3F219AD DRAWIN.

74F224 : This 64-bit active element First-In-First-Out (FIFO) is a monolithic Schottky-clamped transistor-transistor logic (STLL) array organized as 16 words of 4-bits each. A memory system using the 74F224 can be easily expanded in multiples of 15m+1 words or of 4n bits, or both (where n is the number of packages in the horizontal array). However, an external gating is required (see Figure 1). For longer words using 74F224, the IR signals of the first-rank packages and OR signals of the last-rank packages must be ANDed for proper synchronization.The 3-State outputs controlled by a single input (OE) make bus connection and multiplexing easy. TYPE TYPICAL fmax 50MHz 74F224 ORDERING INFORMATION OR.

74F2240 : The 74F2240 and 74F2241 are octal buffers that are ideal for driving dynamic DRAM with impedance matching. The outputs are all capable of sinking 5mA and sourcing up to 15mA. The device features two output enables, each controlling four of the 3-state outputs. TYPICAL PROPAGATION DELAY 4.3ns 4.5ns TYPICAL SUPPLY CURRENT (TOTAL) 37mA 30mA PIN CONFIGURATION 74F2240 OEa 1 Ia0 2 Yb0 3 Ia1 4 Yb1 5 Ia2 6 Yb2 7 Ia3 8 Yb3 9 GND 10 20 VCC 19 OEb 18 Ya0 17 Ib0 16 Ya1 15 Ib1 14 Ya2 13 Ib2 12 Ya3 11 Ib3 SF00561 TYPE 74F2240 74F2241 LOGIC SYMBOL 74F2240 2 4 6 8 17 15 13 11 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F2240N, N74F2241N N74F2240D, .

74F2240 : The 74F2240 is an inverting octal buffer and line driver designed to drive capacitive inputs of MOS memory devices, address and clock lines or act as a low undershoot general purpose bus driver. The 25Ω series resistor in the outputs reduces undershoot and ringing and eliminates the need for external resistors. Features s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs sink 12 mA and source 15 mA s 25Ω series resistors in outputs eliminate the need for external resistors s Designed to drive the capacitive inputs of MOS devices s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74F2240SC 74F2240QC Package Number M20B V20A Package Description 2.

74F2241 : The 74F2240 and 74F2241 are octal buffers that are ideal for driving dynamic DRAM with impedance matching. The outputs are all capable of sinking 5mA and sourcing up to 15mA. The device features two output enables, each controlling four of the 3-state outputs. TYPICAL PROPAGATION DELAY 4.3ns 4.5ns TYPICAL SUPPLY CURRENT (TOTAL) 37mA 30mA PIN CONFIGURATION 74F2240 OEa 1 Ia0 2 Yb0 3 Ia1 4 Yb1 5 Ia2 6 Yb2 7 Ia3 8 Yb3 9 GND 10 20 VCC 19 OEb 18 Ya0 17 Ib0 16 Ya1 15 Ib1 14 Ya2 13 Ib2 12 Ya3 11 Ib3 SF00561 TYPE 74F2240 74F2241 LOGIC SYMBOL 74F2240 2 4 6 8 17 15 13 11 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F2240N, N74F2241N N74F2240D, .

74F2243 : The 74F2243 is a quad bus transmitter/receiver which can be used for 4-line asynchronous 2-way data communications between data busses. It is designed to drive the capacitive inputs of MOS memory drivers, address drivers, clock drivers, and bus-oriented transmitters/receivers. The 25Ω series resistors in the outputs reduce ringing and eliminate the need for external resistors. Features s 25Ω series resistors in outputs eliminate the need for external resistors s 2-Way asynchronous data bus communication s 3-STATE outputs s 12 mA source current s Designed to drive the capacitive inputs of MOS devices Ordering Code: Order Number 74F2243SC Package Number M14A Package Description 14-Lead Small.

74F2244 : The 74F2244 is an octal buffer that is ideal for driving dynamic DRAM with matching impedance. The outputs are all capable of sinking 5mA and sourcing up to 15mA. The device features two output enables, OEa and OEb, each controlling four of the 3–state outputs. TYPICAL PROPAGATION DELAY 4.0ns TYPICAL SUPPLY CURRENT (TOTAL) 30mA TYPE 74F2244 ORDERING INFORMATION ORDER CODE DESCRIPTION 20-pin plastic DIP 20-pin plastic SOL 20-pin plastic SSOP Type II COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F2244N N74F2244D N74F2244DB DRAWING NUMBER SOT146-1 SOT163-1 SOT339-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS Ian, Ibn OEa, OEb Data inputs Output enable inputs (active low) DESCRIP.

74F2244 : The F2244 is an octal buffer/line driver designed to drive the capacitive inputs of MOS memory drivers, address drivers, clock drivers and bus-oriented transmitters/receivers. The 25Ω series resistors in the outputs reduce ringing and eliminate the need for external resistors. Features s 3-STATE outputs drive bus lines or buffer memory address registers s 12 mA source current s 25Ω series resistors in outputs eliminate the need for external resistors. s Designed to drive the capacitive inputs of MOS devices s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74F2244SC 74F2244MSA 74F2244PC Package Number M20B MSA20 N20A Package Description 20-Lead Small Outline Integrated .

74F2244 : The ’F2244 is an octal buffer line driver designed to drive the capacitive inputs of MOS memory drivers address drivers clock drivers and bus-oriented transmitters receivers The 25X series resistors in the outputs reduce ringing and eliminate the need for external resistors Features Y Y Y Y Y TRI-STATE outputs drive bus lines or buffer memory address registers 12 mA source current 25X series resistors in outputs eliminate the need for external resistors Designed to drive the capacitive inputs of MOS devices Guaranteed 4000V minimum ESD protection Commercial 74F2244PC Military Package Number N20B Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line .

74F2244 : This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The 25-Ω resistors in the lower output circuit reduce ringing and eliminate the need for external resistors. The SN74F2244 is characterized for operation from 0°C to 70°C. SN74F2244 25ĆΩ OCTAL BUFFER/DRIVER WITH 3ĆSTATE OUTPUTS SDFS095B − NOVEMBER 1993 − REVISED JANUARY 1996 DW OR N PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 2A1 FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y LH H LL .

74F2245 : The 74F2245 is an octal transceiver featuring non-inverting 3-State bus compatible outputs in both transmit and receive directions. The device features an Output Enable (OE) input for easy cascading and Transmit/Receive (T/R) input for direction control. The 3-State outputs, B0-B7, have been designed to prevent output bus loading if the power is removed from the device. The 30 Ohm series termination on the outputs reduces over/undershoot making them ideal for driving DRAM. TYPE 74F2245 TYPICAL PROPAGATION DELAY 4.0ns A5 A6 A7 GND 10 SF00198 TYPICAL SUPPLY CURRENT (TOTAL) 70mA ORDERING INFORMATION DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL 20-Pin Plastic SSOP COMMERCIAL RANGE VCC .




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