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74F395

Philips
Part Number 74F395
Manufacturer Philips
Description 4-bit cascadable shift register
Published May 28, 2005
Detailed Description Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 FEATURES • 4-bit para...
Datasheet PDF File 74F395 PDF File

74F395
74F395

Overview
Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 FEATURES • 4-bit parallel load shift register • Independent 3-State buffer outputs, Q0–Q3 • Separate Qs output for serial expansion • Asynchronous Master Reset DESCRIPTION The 74F395 is a 4-bit Shift Register with serial and parallel synchronous operating modes and 3-State buffer outputs.
The shifting and loading operations are controlled by the state of the Parallel Enable (PE) input.
When PE is High, data is loaded from the Parallel Data inputs (D0–D3) into the register synchronous with the High-to-Low transition of the Clock input (CP).
When PE is Low, the data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and the data in the register is shifted one bit to the right in the direction (Q0!Q1!Q2!Q3) synchronous with the negative clock transition.
The PE and Data inputs are fully edge-triggered and must be stable one setup prior to the High-to-Low transition of the clock.
The Master Reset (MR) is an asynchronous active-Low input.
When Low, the MR overrides the clock and all other inputs and clears the register.
The 3-state output buffers are designed to drive heavily loaded 3-State buses, or large capacitive loads.
The active-Low Output Enable (OE) controls all four 3-State buffers independent of the register operation.
The data in the register appears at the outputs when OE is Low.
The outputs are in High impedance “OFF” state, which means they will neither drive nor load the bus when OE is High.
The output from the last stage is brought out separately.
This output (Qs) is tied to the Serial Data input (Ds) of the next register for serial expansion applications.
The Qs output is not affected by the 3-State buffer operation.
PIN CONFIGURATION MR Ds D0 D1 D2 D3 PE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0 Q1 Q2 Q3 Qs CP OE SF00940 TYPE 74F395 TYPICAL fMAX 120MHz TYPICAL SUPPLY CURRENT (TOTAL) 32mA ORDERING INFORMATION DESCRIPTION 16-pin pla...


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