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74F574


Part Number 74F574
Manufacturer Fairchild
Title Octal D-Type Flip-Flop
Description The 74F574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information ...
Features s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74F374 s 3-STATE outputs for bus-oriented applications Ordering Code: Order Number 74F574SC 74F574SJ 74F574PC Package Numbe...

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74F573 : The 74F573 is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74F573 is functionally identical to the 74F373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs is transferred to the latch outputs when the Enable (E) input is High. The latch remains transparent to the data input while E is High and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS m.

74F573 : The 74F573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device is functionally identical to the 74F373 but has different pinouts. Features s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74F373 s 3-STATE outputs for bus interfacing s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74F573SC 74F573SJ 74F573PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ T.

74F573 : The ’F573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs This device is functionally identical to the ’F373 but has different pinouts Features Y Y Y Y Y Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to ’F373 TRI-STATE outputs for bus interfacing Guaranteed 4000V minimum ESD protection Commercial 74F573PC Military Package Number N20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small .

74F573 : These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54F573 J PACKAGE SN74F573 DW OR N PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE SN54F573 FK PACKAGE (TOP VIEW) 1Q VCC OE 1D 2D The eight latches of the ′F573 are transparent D-type latches. While the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs a.

74F574 : The 74F573 is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74F573 is functionally identical to the 74F373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs is transferred to the latch outputs when the Enable (E) input is High. The latch remains transparent to the data input while E is High and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS m.

74F574 : The ’F574 is a high-speed low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE) The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition This device is functionally identical to the ’F374 except for the pinouts Features Y Y Y Y Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to ’F374 TRI-STATE outputs for bus-oriented applications Commercial 74F574PC Military Package Number N20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20.

74F574 : This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. DW OR N PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 CLK The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs. A buffered output enable (OE) input can be used to place the eight outputs in eith.

74F579 : The 74F579 is a fully synchronous 8-stage Up/Down Counter with multiplexed 3-State I/O ports for bus-oriented applications. It features a preset capability for programmable operation, carry look-ahead for easy cascading and a U/D input to control the direction of counting. All state changes, except for the case of asynchronous reset, are initiated by the rising edge of the clock. TC output is not recommended for use as a clock or asynchronous reset due to the possibility of decoding spikes. PIN CONFIGURATION CP I/O0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 MR SR CEP CET VCC TC U/D PE CS OE SF01085 ORDERING INFORMATION TYPE 74F579 TYPICAL fM.

74F579 : The 74F579 is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O ports for bus-oriented applications. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock. Features s Multiplexed 3-STATE I/O ports s Built-in lookahead carry capability s Count frequency 100 MHz typical s Supply current 75 mA typical s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74F579SC 74F579SJ 74F579PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integ.

74F579 : .




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