DatasheetsPDF.com

74F64

Part Number 74F64
Manufacturer Philips
Title 4-2-3-2-input AND-OR-invert gate
Description 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F64N N74F64D PKG. DWG. # Dg Dh Di SOT27-1 SOT108-1 ...
Features 8 VCC = Pin 14 GND = Pin 7 & 10 SF00095 SF00096 1996 Mar 14 2 853
  –0334 16574 Philips Semiconductors Product specification 4-2-3-2-input AND-OR-invert gate 74F64 LOGIC DIAGRAM Da Db Dc Dd De Df Dg Dh Di Dj Dk VCC = Pin 14 GND = Pin 7 2 3 1 13 12 11 8 4 5 6 9 10 Q SF00097 FUNCTION TABLE...

File Size 72.64KB
Datasheet 74F64 PDF File







Similar Datasheet

74F604 : The 74F604 multiplexed latch is ideal for storing data from two input buses, A or B, and providing data from either the A or B latches to the output bus. Organized as 8-bit A and B latches, the latch outputs are connected by pairs to eight 2-input multiplexers. A Select (SELECT A/B) input determines whether the A or B latch contents are multiplexed to the eight 3-State outputs. Data entered from the B inputs are selected when SELECT A/B is Low; data from the A inputs are selected when SELECT A/B is High. Data enters the latches when the Latch Enable (LE) input is Low and is latched on the LE rising edge. The outputs are enabled when LE is High and disabled when LE is Low. A2 B2 A3 B3 Q3 Q2 .

74F620 : The 74F620 is an octal transceiver featuring inverting 3-State bus-compatible outputs in both send and receive directions. The outputs are capable of sinking 64mA and sourcing up to 15mA, providing very good capacitive drive characteristics. The 74F623 is a non-inverting version of the 74F620. These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the TYPE 74F620 74F623 ORDERING INFORMATION DESCRIPTION 20-pin plastic DIP 20-pin plastic SO.

74F620 : These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA and have 3STATE outputs. Dual enable pins (GAB, GBA) allow data transmission from the A bus to the B bus or from the B bus to the A bus. The 74F620 is an inverting option of the 74F623. Features s Designed for asynchronous two-way data flow between busses s Outputs sink 64 mA s Dual enable inputs control direction of data flow s Guaranteed 4000V minimum ESD protection s 74F620 is an inverting option of the 74F623 Ordering Code: Order Number 74F620PC 74F623SC 74F623PC Package Number N20A M20B N20A Package Description 20-Lead Plastic Dual-I.

74F621 : The 74F621 is an octal transceiver featuring non-inverting open collector bus-compatible outputs in both send and receive directions. The outputs are capable of sinking 64mA, providing very good capacitive drive characteristics. This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the Enable inputs (OEBA and OEAB). The Enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration giv.

74F623 : These octal bus transceivers are designed for asynchronous communication between data buses. The control function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output enable (OEAB and OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability of storing data by simultaneously enabling OEAB and OEBA. Each output reinforces its input in this configuration. When both OEAB and OEBA are enabled and all other data sources to the .

74F623 : The 74F620 is an octal transceiver featuring inverting 3-State bus-compatible outputs in both send and receive directions. The outputs are capable of sinking 64mA and sourcing up to 15mA, providing very good capacitive drive characteristics. The 74F623 is a non-inverting version of the 74F620. These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the TYPE 74F620 74F623 ORDERING INFORMATION DESCRIPTION 20-pin plastic DIP 20-pin plastic SO.

74F64 : This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function. Ordering Code: Order Number 74F64SC 74F64SJ 74F64PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Unit Loading/Fan Out U.L. Pin Names An, Bn, Cn, Dn O Description HIGH/LOW Inputs Output 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −1.

74F64 : This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function Commercial 74F64PC Military Package Number N14A Package Description 14-Lead (0 300 Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0 150 Wide) Molded Small Outline JEDEC 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F64DM (Note 2) 74F64SC (Note 1) 54F64FM (Note 2) 54F64LM (Note 2) Note 1 Devices also available in 13 J14A M14A W14B E20A reel Use suffix e SCX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbol IEEE IEC Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC .

74F640 : The 74F640 is an octal transceiver featuring inverting 3-State bus compatible outputs in both transmit and receive directions. The B port outputs are capable of sinking 64mA and sourcing 15mA, providing very good capacitive drive characteristics. The device features an Output Enable (OE) input for easy cascading and Transmit/Receiver (T/R) input for direction control. The 3-State outputs, B0–B7, have been designed to prevent output bus loading if the power is removed from the device. A7 GND 10 SF00198 TYPE 74F640 TYPICAL PROPAGATION DELAY 3.5ns TYPICAL SUPPLY CURRENT (TOTAL) 78mA ORDERING INFORMATION DESCRIPTION 20-pin plastic DIP 20-pin plastic SOL COMMERCIAL RANGE VCC = 5V ±10%, Tam.

74F640 : These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T/R) input. The 74F645 is a high speed/low power version of the 74F245. The 74F640 is an inverting option of the 74F645. Features s Designed for asynchronous two-way data flow between busses s Outputs sink 64 mA s Transmit/receive (T/R) input controls the direction of data flow s 74F645 is a lower power, faster version of the 74F245 s 74F640 is an inverting option of the 74F645 Ordering Code: Order Number 74F640SC 74F640.

74F641 : 20-pin plastic DIP 20-pin plastic SOL COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F641N N74F641D PKG DWG # SOT146-1 SOT163-1 • Octal bidirectional bus interface • Common Output Enable for both Transmit and Receive modes • Open collector outputs sink 64mA • —74F641, non-inverting —74F642, inverting TYPE 74F641 74F642 TYPICAL PROPAGATION DELAY 8.0ns 8.5ns TYPICAL SUPPLY CURRENT (TOTAL) 69mA 52mA INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0 - A7, B0 - B7 T/R OE A0 - A7 B0 - B7 Data inputs Transmit/Receive input Output Enable inputs Data outputs Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.033 2.0/0.067 2.0/0.067 OC/40 OC/106.7 LOAD VALUE HIGH/LOW 20µA/20µA 40µA/40µA 4.

74F642 : 20-pin plastic DIP 20-pin plastic SOL COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F641N N74F641D PKG DWG # SOT146-1 SOT163-1 • Octal bidirectional bus interface • Common Output Enable for both Transmit and Receive modes • Open collector outputs sink 64mA • —74F641, non-inverting —74F642, inverting TYPE 74F641 74F642 TYPICAL PROPAGATION DELAY 8.0ns 8.5ns TYPICAL SUPPLY CURRENT (TOTAL) 69mA 52mA INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0 - A7, B0 - B7 T/R OE A0 - A7 B0 - B7 Data inputs Transmit/Receive input Output Enable inputs Data outputs Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.033 2.0/0.067 2.0/0.067 OC/40 OC/106.7 LOAD VALUE HIGH/LOW 20µA/20µA 40µA/40µA 4.

74F645 : These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T/R) input. The 74F645 is a high speed/low power version of the 74F245. The 74F640 is an inverting option of the 74F645. Features s Designed for asynchronous two-way data flow between busses s Outputs sink 64 mA s Transmit/receive (T/R) input controls the direction of data flow s 74F645 is a lower power, faster version of the 74F245 s 74F640 is an inverting option of the 74F645 Ordering Code: Order Number 74F640SC 74F640.

74F646 : The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes high. Output enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or both. The select (SAB, SBA) pins determine whether data is stored or transferred through the device in real–time. The DIR determines which bus will.

74F646 : These devices consist of bus transceiver circuits with 3STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control G is A.

74F646 : These devices consist of bus transceiver circuits with TRISTATE D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level Control G and direction pins are provided to control the transceiver function In the transceiver mode data present at the high impedance port may be stored in either the A or the B register or in both The select controls can multiplex stored and real-time (transparent mode) data The direction control determines which bus will receive data when the enable control G is Active .




Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)