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SP8853


Part Number SP8853
Manufacturer Mitel Networks
Title 13GHz Professional Synthesiser
Description Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A co...
Features s Improved Digital Phase Detector Eliminates ‘Dead Band’ Effects s Low Operating Power, Typically 175mW s 1
·3GHz Operating Frequency s Complete Phase Locked Loop s High Input Sensitivity s Programmed throughThree-Wire Bus s Wide Range of Reference Division Ratios s Local Storage for Two Frequency Wo...

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Datasheet SP8853 PDF File








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SP8852 : These are the inputs to the 16-bit data bus. When pin 38 is high the data goes to the buffers for the A counter, M counter and phase detector gain. When pin 38 is low the data goes to the buffers for the reference counter and the phase detector state (see Table 4). Open circuit = 1 (high) on these pins. Data is transparent from pins to the selected buffers when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indi.

SP8852D : Obsolescence Notice This product is obsolete. This information is available for your convenience only. www.DataSheet4U.com For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ SP8852D PACKAGE DETAILS Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre. 17.27/17.78 (0.680/0.700) 16.33/16.81 (0.643/0.662) 12.45/12.95 (0.490/0.510) 0.51 (0.02) NOM AT 45° INDEX CORNER 16.33/16.81 (0.643/0.662) 17.27/17.78 (0.680/0.700) 0.76MM(0.030 ″) 0.43MM(0.017 ″) 1.27/(0.050) NOM  1.02MM/(0.040I )NOM 45° AT 3 PLACES 0.89(0.035) 03.05/3.43 (0.

SP8852E : These are the inputs to the 16-bit data bus. When pin 38 is high the data goes to the buffers for the A counter, M counter and phase detector gain. When pin 38 is low the data goes to the buffers for the reference counter and the phase detector state (see Table 4). Open circuit = 1 (high) on these pins. Data is transparent from pins to the selected buffers when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indi.

SP8852E : These are the inputs to the 16-bit data bus. When pin 38 is high the data goes to the buffers for the A counter, M counter and phase detector gain. When pin 38 is low the data goes to the buffers for the reference counter and the phase detector state (see Table 4). Open circuit = 1 (high) on these pins. Data is transparent from pins to the selected buffers when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indi.

SP8852EIGHCAR : These are the inputs to the 16-bit data bus. When pin 38 is high the data goes to the buffers for the A counter, M counter and phase detector gain. When pin 38 is low the data goes to the buffers for the reference counter and the phase detector state (see Table 4). Open circuit = 1 (high) on these pins. Data is transparent from pins to the selected buffers when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indi.

SP8852EKGHCAR : These are the inputs to the 16-bit data bus. When pin 38 is high the data goes to the buffers for the A counter, M counter and phase detector gain. When pin 38 is low the data goes to the buffers for the reference counter and the phase detector state (see Table 4). Open circuit = 1 (high) on these pins. Data is transparent from pins to the selected buffers when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indi.

SP8853 : Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division. A programmable divider of this type has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21). In the SP8853, the dual modulus front end prescaler is a dual N ratio device, capable of being statically switched between 416/17 and 48/9 ratios. The controlling A counter is of four-bit design, allowing a maximum count sequence of 15 (2421), which begins with the start of the M counter sequence and stops when it has co.

SP8853A : Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division. A programmable divider of this type has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21). In the SP8853, the dual modulus front end prescaler is a dual N ratio device, capable of being statically switched between 416/17 and 48/9 ratios. The controlling A counter is of four-bit design, allowing a maximum count sequence of 15 (2421), which begins with the start of the M counter sequence and stops when it has co.

SP8853AHC : Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division. A programmable divider of this type has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21). In the SP8853, the dual modulus front end prescaler is a dual N ratio device, capable of being statically switched between 416/17 and 48/9 ratios. The controlling A counter is of four-bit design, allowing a maximum count sequence of 15 (2421), which begins with the start of the M counter sequence and stops when it has co.

SP8853B : Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division. A programmable divider of this type has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21). In the SP8853, the dual modulus front end prescaler is a dual N ratio device, capable of being statically switched between 416/17 and 48/9 ratios. The controlling A counter is of four-bit design, allowing a maximum count sequence of 15 (2421), which begins with the start of the M counter sequence and stops when it has co.

SP8853BHC : Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division. A programmable divider of this type has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21). In the SP8853, the dual modulus front end prescaler is a dual N ratio device, capable of being statically switched between 416/17 and 48/9 ratios. The controlling A counter is of four-bit design, allowing a maximum count sequence of 15 (2421), which begins with the start of the M counter sequence and stops when it has co.

SP8854 : These pins are the data inputs to set the RF divider ratio (MN1A). High is open circuit on these pins. Data is transparent from pins to RF buffer when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give an external indication of phase lock. A capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indi.

SP8854D : Obsolescence Notice This product is obsolete. This information is available for your convenience only. www.DataSheet4U.com For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ SP8854D PACKAGE DETAILS Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre. 17.27/17.78 (0.680/0.700) 16.33/16.81 (0.643/0.662) 12.45/12.95 (0.490/0.510) 0.51 (0.02) NOM AT 45° INDEX CORNER 16.33/16.81 (0.643/0.662) 17.27/17.78 (0.680/0.700) 0.76MM(0.030 ″) 0.43MM(0.017 ″) 1.27/(0.050) NOM  1.02MM/(0.040I )NOM 45° AT 3 PLACES 0.89(0.035) 03.05/3.43 (0.

SP8854E : These pins are the data inputs to set the RF divider ratio (MN1A). High is open circuit on these pins. Data is transparent from pins to RF buffer when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give an external indication of phase lock. A capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indi.

SP8854E : SP8854E These pins are the data inputs to set the RF divider ratio (MN1A). High is open circuit on these pins. Data is transparent from pins to RF buffer when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give an external indication of phase lock. A capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase.

SP8854EIGHCAR : These pins are the data inputs to set the RF divider ratio (MN1A). High is open circuit on these pins. Data is transparent from pins to RF buffer when pin 39 (STROBE) is high and frozen in buffers when pin 39 is low. Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give an external indication of phase lock. A capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indi.




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