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MC145193

Part Number	MC145193
Manufacturer	Motorola
Description	1.1 GHZ PLL FREQUENCY SYNTHESIZER
Published	Jun 12, 2005
Detailed Description	Order this document by MC145193/D MC145193 1.1 GHz PLL Frequency Synthesizer The MC145193 is recommended for new design...
Datasheet	MC145193 PDF File

Overview

Order this document by MC145193/D MC145193 1.
1 GHz PLL Frequency Synthesizer The MC145193 is recommended for new designs and offers reduced power consumption.
The counters are programmed via a synchronous serial port which is SPI compatible.
The serial port is byte-oriented to facilitate control via an MCU.
Due to the innovative BitGrabber Plus™ registers, the MC145193 may be cascaded with other peripherals featuring BitGrabber Plus without requiring leading dummy bits or address bits in the serial data stream.
In addition, BitGrabber Plus peripherals may be cascaded with existing BitGrabber™ peripherals.
The device features a single–ended current source/sink phase detector A output and a double–ended phase detector B output.
Both phase detectors have linear transfer functions (no dead zones).
The maximum current of the single–ended phase detector output is determined by an external resistor tied from the Rx pin to ground.
This current can be varied via the serial port.
Slew–rate control is provided by a special driver designed for the REFout pin.
This minimizes interference caused by REFout.
This part includes a differential RF input that may be operated in a single–ended mode.
Also featured are on–board support of an external crystal and a programmable reference output.
The R, A, and N counters are fully programmable.
The C register (configuration register) allows the part to be configured to meet various applications.
A patented feature allows the C register to shut off unused outputs, thereby minimizing system noise and interference.
In order to have consistent lock times and prevent erroneous data from being loaded into the counters, on–board circuitry synchronizes the update of the A register if the A or N counters are loading.
Similarly, an update of the R register is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented to the three counters (R, A, and N) simultaneously.
PLL FREQUENCY SYNTHESIZER ...

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