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MAX3890

Maxim
Part Number MAX3890
Manufacturer Maxim
Description +3.3V / 2.5Gbps / SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs
Published Jun 13, 2005
Detailed Description 19-1498; Rev 0; 6/99 KIT ATION EVALU E L B AVAILA +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and L...
Datasheet PDF File MAX3890 PDF File

MAX3890
MAX3890

Overview
19-1498; Rev 0; 6/99 KIT ATION EVALU E L B AVAILA +3.
3V, 2.
5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs General Description The MAX3890 serializer is ideal for converting 16-bitwide, 155Mbps parallel data to 2.
5Gbps serial data in ATM and SDH/SONET applications.
Operating from a single +3.
3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers PECL serial data and clock outputs.
A fully integrated PLL synthesizes an internal 2.
5GHz serial clock from a 155.
52MHz, 77.
76MHz, 51.
84MHz, or 38.
88MHz reference clock.
A loopback data output is provided to facilitate system diagnostic testing.
The MAX3890 is available in the extended temperature range (-40°C to +85°C) in a 64-pin TQFP exposedpaddle (EP) package.
o Single +3.
3V Supply o 495mW Power Consumption o Exceeds ANSI, ITU, and Bellcore Specifications o 155Mbps (16-bit wide) Parallel to 2.
5Gbps Serial Conversion o Clock Synthesis for 2.
5Gbps o Multiple Clock Reference Frequencies (155.
52MHz, 77.
76MHz, 51.
84MHz, 38.
88MHz) o LVDS Parallel Clock and Data Inputs o Additional High-Speed Output for System Loopback Testing Features MAX3890 Applications 2.
5Gbps SDH/SONET Transmission Systems 2.
5Gbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross-Connects ATM Backplanes PART Ordering Information TEMP.
RANGE PIN-PACKAGE 64 TQFP-EP* MAX3890ECB -40°C to +85°C *EP = Exposed Paddle Pin Configuration appears at end of data sheet.
Typical Operating Circuit 155MHz REF.
CLOCK INPUT +3.
3V +3.
3V TTL +3.
3V 130Ω 130Ω VCC 82Ω 82Ω +3.
3V PDI0+ RCLK+ RCLK- CLKSET PDI0PDI15+ OVERHEAD GENERATION PDI15PCLKI+ PCLKIPCLKO+ PCLKOGND VCC SOS SDO+ SDO- MAX3890 130Ω SCLKO+ SCLKOFIL+ FILSLBO+ SLBO82Ω 82Ω 130Ω MAX3867 330nF OPTIONAL CONNECTION TO MAX3880 FOR SYSTEM LOOPBACK TESTING.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50Ω).
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