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SPT7860

Fairchild Semiconductor
Part Number SPT7860
Manufacturer Fairchild Semiconductor
Description 10-BIT / 40 MSPS / 175 mW A/D CONVERTER
Published Sep 27, 2005
Detailed Description SPT7860 10-BIT, 40 MSPS, 175 mW A/D CONVERTER TECHNICAL DATA MAY 25, 2001 FEATURES • • • • • • • • • • Monolithic 40 MS...
Datasheet PDF File SPT7860 PDF File

SPT7860
SPT7860

Overview
SPT7860 10-BIT, 40 MSPS, 175 mW A/D CONVERTER TECHNICAL DATA MAY 25, 2001 FEATURES • • • • • • • • • • Monolithic 40 MSPS converter 175 mW power dissipation On-chip track-and-hold Single +5 V power supply TTL/CMOS outputs 5 pF input capacitance Low cost Tri-state output buffers High ESD protection: 3,500 V minimum Selectable +3 V or +5 V logic I/O APPLICATIONS • All high-speed applications where low power dissipation is required • Video imaging • Medical imaging • Radar receivers • IR imaging • Digital communications GENERAL DESCRIPTION The SPT7860 is a 10-bit monolithic, low-cost, ultralowpower analog-to-digital converter capable of minimum word rates of 40 MSPS.
The on-chip track-and-hold function assures very good dynamic performance without the need for external components.
The input drive requirements are minimized due to the SPT7860’s low input capacitance of only 5 pF.
Power dissipation is extremely low at only 175 mW typical at 40 MSPS with a power supply of +5.
0 V.
The digital outputs are +3 V or +5 V, and are user selectable.
The SPT7860 is pin-compatible with an entire family of 10-bit, CMOS converters (SPT7835/40/50/55/60/61), which simplifies upgrades.
The SPT7860 has incorporated proprietary circuit design* and CMOS processing technologies to achieve its advanced performance.
Inputs and outputs are TTL/CMOS-compatible to interface with TTL/CMOS logic systems.
Output data format is straight binary.
The SPT7860 is available in 28-lead SOIC and 32-lead small (7 mm square) TQFP packages over the commercial temperature range.
*Patent pending BLOCK DIAGRAM ADC Section 1 AIN 1:16 Mux T/H AutoZero CMP 11-Bit SAR 11 11 D10 Overrange D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 P1 P2 Timing P15 and Control Enable P16 DAC CLK In .
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ADC Section 15 ADC Section 2 ADC Section 16 T/H AutoZero CMP .
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11-Bit SAR 11 DAC 11 .
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11 11 11-Bit 16:1 Mux/ Error Correction Data Valid Ref In Reference Ladder D0 (LSB) VREF ABSOLUTE MAXIMUM RATINGS (Beyond w...


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