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MT9072

Part Number	MT9072
Manufacturer	Zarlink Semiconductor
Description	Octal T1/E1/J1 Framer
Published	Oct 26, 2005
Detailed Description	MT9072 Octal T1/E1/J1 Framer Data Sheet Features • • • • Eight fully independent, T1/E1/J1 framers 3.3 V supply with 5 V...
Datasheet	MT9072 PDF File

Overview

MT9072 Octal T1/E1/J1 Framer Data Sheet Features • • • • Eight fully independent, T1/E1/J1 framers 3.
3 V supply with 5 V tolerant inputs Selectable 2.
048 Mbit/s or 8.
192 Mbit/s serial buses for both data and signaling Framing Modes: - T1: D4, ESF, T1DM - E1: Basic Framing, CRC4 multiframing and Signaling Multiframing Supports Inverse Mux for ATM Timeslot assignable HDLC IEEE-1149.
1 (JTAG) test port T1/E1/J1 add/drop multiplexers V5.
1 and V5.
2 access network interfaces CO and PBX equipment interfaces Primary rate IDSN nodes Ordering Information MT9072AB MT9072AV 208 Pin LQFP 220 Pin LBGA October 2004 -40° C to +85 ° C • • Digital Cross-connect Systems (DCS) Wireless base stations • • • • • • • Description The MT9072 is a multi-port T1/E1/J1 framing device that integrates eight fully independent, feature rich framers.
The device is software selectable between T1, E1 or J1 modes and meets the latest relevant recommendations and standards from Telcordia, ANSI, ETSI and ITU-T.
An extensive suite of features make the MT9072 very flexible and suitable for a wide variety of applications around the globe.
Applications TxDL[0] TxDLC[0] DSTi [0] CSTi [0] TxCL [0] TPOS[0] TNEG[0] ST-BUS Interface ST-BUS Loopback Payload Loopback Transmit Framing, Error and Test Signal Generation CKi[0] FPi[0] National Bit Buffer CAS Buffer Remote Loopback ST-BUS Data Link Circuit Timing Digital Loopback RPOS[0] RNEG[0] DSTo[0] CSTo[0] ST-BUS Interface Receive Framing, Performance Monitoring, Alarm Detection, 2 Frame Slip Buffer RxBF[0] EXCLi[0] FRAMER 0 FRAMER 1 FRAMER 2 FRAMER 3 FRAMER 4 FRAMER 5 FRAMER 6 FRAMER 7 RxDLC[0] RxDL[0] RxMF[0] Microprocessor Interface IEEE 1149.
1 TAP Common Control and Power D15~D0 A11~A0 DS RW CS IRQ IM TDI TDO TMS TCK TRST RESET TAIS VDD VSS T1-3 TxMF Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor In...

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