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8086

Intel
Part Number 8086
Manufacturer Intel
Description 16-Bit HMOS Microprocessor
Published May 16, 2006
Detailed Description 8086 16-BIT HMOS MICROPROCESSOR 8086/8086-2/8086-1 Y Direct Addressing Capability 1 MByte of Memory Y Architecture Desi...
Datasheet PDF File 8086 PDF File

8086
8086

Overview
8086 16-BIT HMOS MICROPROCESSOR 8086/8086-2/8086-1 Y Direct Addressing Capability 1 MByte of Memory Y Architecture Designed for Powerful Assembly Language and Efficient High Level Languages Y 14 Word, by 16-Bit Register Set with Symmetrical Operations Y 24 Operand Addressing Modes Y Bit, Byte, Word, and Block Operations Y 8 and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal Including Multiply and Divide Y Range of Clock Rates: 5 MHz for 8086, 8 MHz for 8086-2, 10 MHz for 8086-1 Y MULTIBUS System Compatible Interface Y Available in EXPRESS – Standard Temperature Range – Extended Temperature Range Y Available in 40-Lead Cerdip and Plastic Package (See Packaging Spec.
Order ›231369) The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz.
The CPU is implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin CERDIP or plastic package.
The 8086 operates in both single processor and multiple processor configurations to achieve high performance levels.
Figure 1.
8086 CPU Block Diagram 231455 – 1 40 Lead 231455 – 2 Figure 2.
8086 Pin Configuration September 1990 Order Number: 231455-005 8086 Table 1.
Pin Description The following pin function descriptions are for 8086 systems in either minimum or maximum mode.
The ‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers).
Symbol AD15 – AD0 A19/S6, A18/S5, A17/S4, A16/S3 BHE/S7 RD Pin No.
2–16, 39 35 – 38 34 32 Type I/O O O O Name and Function ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1), and data (T2, T3, TW, T4) bus.
A0 is analogous to BHE for the lower byte of the data bus, pins D7 – D0.
It is LOW during T1 when a byte is to be transferred on the lower portion of the bus in memory or I/O operations.
Eight-bit oriented devices tied to the lower half would normally use A0 to condition chip se...


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