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MC74ACT574


Part Number MC74ACT574
Manufacturer ON Semiconductor
Title Octal D Flip-Flop
Description The MC74AC574/74ACT574 consists of eight edgetriggered flip−flops with individual D−type inputs and 3−state true outputs. The buffered clock and b...
Features
• Inputs and Outputs on Opposite Sides of Package Allowing Easy Interface with Microprocessors
• Useful as Input or Output Port for Microprocessors
• Functionally Identical to MC74AC374/74ACT374
• 3-State Outputs for Bus-Oriented Applications
• Outputs Source/Sink 24 mA
• ′ACT574 Has TTL Compatible ...

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MC74ACT573 : MC74AC573, MC74ACT573 Octal Buffer/Line Driver with 3-State Outputs The MC74AC573/74ACT573 is a high−speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The MC74AC573/74ACT573 is functionally identical to the MC74AC373/74ACT373 but has inputs and outputs on opposite sides. Features • Inputs and Outputs on Opposite Sides of Package Allowing Easy Interface with Microprocessors • Useful as Input or Output Port for Microprocessors • Functionally Identical to MC74AC373/74ACT373 • 3−State Outputs for Bus Interfacing • Outputs Source/Sink 24 mA • ′ACT573 Has TTL Compatible Inputs • These are Pb−Free Devices VCC O0 O1 O2 O3 O4 O5 O6 O7 LE 20 19 18.

MC74ACT573 : The MC74AC573/74ACT574 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 D.

MC74ACT574 : The MC74AC574/74ACT574 consists of eight edgetriggered flip-flops with individual D-type inputs and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. FUNCTION TABLE Inputs OE H H H H L L L L CP H H D L H L H L H L H Internal Q NC NC L H L H NC NC Outputs Funct.




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