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PDU54

Part Number	PDU54
Manufacturer	Data Delay Devices
Description	ECL-INTERFACED PROGRAMMABLE DELAY LINE
Published	Nov 18, 2006
Detailed Description	www.DataSheet4U.com PDU54 4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU54) FEATURES • • • • • Digitally pr...
Datasheet	PDU54 PDF File

Overview

www.
DataSheet4U.
com PDU54 4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU54) FEATURES • • • • • Digitally programmable in 16 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully 100K-ECL interfaced & buffered Available in 24-pin DIP (600 mil) socket or SMD PDU54-xx DIP PDU54-xxM Military DIP N/C N/C GND N/C N/C N/C N/C N/C GND OUT N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 data 3 delay devices, inc.
PACKAGES IN N/C VEE A3 N/C N/C A2 A1 VEE A0 N/C N/C  N/C N/C GND N/C N/C N/C N/C N/C GND OUT N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 IN N/C VEE A3 N/C N/C A2 A1 VEE A0 N/C N/C PDU54-xxC4 SMD PDU54-xxMC4 Mil SMD FUNCTIONAL DESCRIPTION The PDU54-series device is a 4-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A3-A0) according to the following formula: TDA = TD0 + TINC * A PIN DESCRIPTIONS IN OUT A3-A0 VEE GND Signal Input Signal Output Address Bits -5 Volts Ground where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device.
The incremental delay is specified by the dash number of the device and can range from 100ps through 3000ps, inclusively.
The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS • • • • • • • • • Total programmed delay tolerance: 5% or 40ps, whichever is greater Inherent delay (TD0): 3.
3ns typical Address to input setup (TAIS): 2.
9ns Operating temperature: 0° to 85° C Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VEE: -5VDC ± 0.
7V Power Supply Current: -300ma typical (50Ω to -2V) Minimum pulse width: 3ns or 10% of total delay, whichever is greater Minimum period: 8ns or 2 x pulse width, whichever is greater A i-1 PW IN IN TDA OUT Figure 1: Timing Diagram 1997 Data Delay Devices DASH NUMBER SPECIFICATIONS Part Number PD...

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