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AD9942

Part Number	AD9942
Manufacturer	Analog Devices
Description	14-Bit CCD Signal Processor
Published	Jan 20, 2007
Detailed Description	www.DataSheet4U.com Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing™ Core AD9942 FEATURES 40 MHz correl...
Datasheet	AD9942 PDF File

Overview

www.
DataSheet4U.
com Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing™ Core AD9942 FEATURES 40 MHz correlated double sampler (CDS) 0 dB to 18 dB, 9-bit variable gain amplifier (VGA) 40 MSPS analog-to-digital converter (ADC) Optical black clamp (CLPOB) with variable level control Complete on-chip timing driver Precision Timing core with <550 ps resolution On-chip 3 V horizontal and RG drivers 4-phase H-clock mode 100-lead, 9 mm × 9 mm, CSP_BGA package GENERAL DESCRIPTION The AD9942 is a highly integrated dual-channel CCD signal processor for digital still camera applications.
Each channel is specified at pixel rates of up to 40 MHz.
The AD9942 consists of a complete analog front end with analog-to-digital conversion, combined with a programmable timing driver.
The Precision Timing core allows high speed clocks to be adjusted with 550 ps resolution.
The analog front end uses black level clamping and includes a VGA, a 40 MSPS ADC, and a CDS.
The timing driver provides the high speed CCD clock drivers for RG_A and RG_B, as well as the H1A to H4A and H1B to H4B outputs.
The 6-wire serial interface is used to program the AD9942.
Available in a space-saving, 9 mm × 9 mm, CSP_BGA package, the AD9942 is specified over an operating temperature range of −25°C to +85°C.
APPLICATIONS Signal processor for dual-channel CCD outputs Digital still cameras Digital video cameras High speed digital imaging applications FUNCTIONAL BLOCK DIAGRAM REFT_A REFB_A REFT_B REFB_B AD9942 VREF_A VREF_B 14 CCDIN_A CDS VGA 0dB ~ 18dB ADC CLAMP CLAMP 0dB ~ 18dB DOUT_A CCDIN_B CDS VGA ADC 14 DOUT_B INTERNAL CLOCKS RG_A RG_B H1A TO H4A H1B TO H4B 4 4 SYNC GENERATOR INTERNAL REGISTERS SCK_A SCK_B 05240-001 HORIZONTAL DRIVERS PRECISION TIMING CORE CLI_A CLI_B HD_A VD_A HD_B VD_B SL_A SDATA_A SL_B SDATA_B Figure 1.
Rev.
A Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its u...

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