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82C288

Intel Corporation
Part Number 82C288
Manufacturer Intel Corporation
Description BUS CONTROLLER
Published Nov 5, 2007
Detailed Description www.DataSheet4U.com M82C288 BUS CONTROLLER FOR M80286 PROCESSORS (M82C288-10 M82C288-8 M82C288-6) Military Y Provides ...
Datasheet PDF File 82C288 PDF File

82C288
82C288

Overview
www.
DataSheet4U.
com M82C288 BUS CONTROLLER FOR M80286 PROCESSORS (M82C288-10 M82C288-8 M82C288-6) Military Y Provides Commands and Controls for Local and System Bus Wide Flexibility in System Configurations Implemented in High Speed CHMOS III Technology Fully Compatible with the HMOS M82288 Y Y Y Fully Static Device Single a 5V Supply Available in 20 Pin Cerdip Package (See Packaging Spec Order 231369) Y Y Y The Intel M82C288 Bus Controller is a 20-pin CHMOS III component for use in M80C286 microsystems The M82C288 is fully compatible with its predecessor the HMOS M82288 The bus controller is fully static and supports a low power mode The bus controller provides command and control outputs with flexible timing options Separate command outputs are used for memory and I O devices The data bus is controlled with separate data enable and direction control signals Two modes of operation are possible via a strapping option MULTIBUS Compatible bus cycles and high speed bus cycles 20 Pin Cerdip Package 271077 – 2 Figure 2 M82C288 Pin Configuration 271077 – 1 Figure 1 M82C288 Block Diagram November 1991 Order Number 271077-006 www.
DataSheet4U.
com M82C288 Table 1 Pin Description The following pin function descriptions are for the M82C288 bus controller Symbol Type CLK I Name and Function SYSTEM CLOCK provides the basic timing control for the M82C288 in an M80286 microsystem Its frequency is twice the internal processor clock frequency The falling edge of this input signal establishes when inputs are sampled and command and control outputs change BUS CYCLE STATUS starts a bus cycle and along with M IO defines the type of bus cycle These inputs are active LOW A bus cycle is started when either S1 or S0 is sampled LOW at the falling edge of CLK Setup and hold times must be met for proper operation M80286 Bus Cycle Status Definition M IO 0 0 0 0 1 1 1 1 M IO I S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Interrupt Acknowledge I O Read I O Write None Idle Halt or Shutdown...


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