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74AUP1T58

Part Number	74AUP1T58
Manufacturer	NXP
Description	Low-power Configurable Gate
Published	Jul 2, 2009
Detailed Description	www.DataSheet4U.com 74AUP1T58 Low-power conﬁgurable gate with voltage-level translator Rev. 01 — 6 March 2008 Product d...
Datasheet	74AUP1T58 PDF File

Overview

www.
DataSheet4U.
com 74AUP1T58 Low-power conﬁgurable gate with voltage-level translator Rev.
01 — 6 March 2008 Product data sheet 1.
General description The 74AUP1T58 provides low-power, low-voltage conﬁgurable logic gate functions.
The output state is determined by eight patterns of 3-bit input.
The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter and buffer.
All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.
3 V to 3.
6 V.
The 74AUP1T58 is designed for logic-level translation applications with input switching levels that accept 1.
8 V low-voltage CMOS signals, while operating from either a single 2.
5 V or 3.
3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from 3.
6 V to 2.
3 V.
This device is fully speciﬁed for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range.
2.
Features I Wide supply voltage range from 2.
3 V to 3.
6 V I High noise immunity I ESD protection: N HBM JESD22-A114E Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 1.
5 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages up to 3.
6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C www.
DataSheet4U.
com NXP Semiconductors 74AUP1T58 Low-power conﬁgurable gate with voltage-level translator 3.
Ordering information Table 1.
Ordering information Package Temperature range Name 74AUP1T58GW 74AUP1T58GM 74AUP1T58GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to...

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