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YSS944

YAMAHA
Part Number YSS944
Manufacturer YAMAHA
Description (YSS940 - YSS944) ADAMB Advanced Digital Audio Multi channel decode processor
Published Jun 23, 2011
Detailed Description YSS944/943/940 ADAMB Advanced Digital Audio Multi channel decode processor „ Outline The YSS944 (ADAMB-f)/YSS943 (ADAMB-...
Datasheet PDF File YSS944 PDF File

YSS944
YSS944

Overview
YSS944/943/940 ADAMB Advanced Digital Audio Multi channel decode processor „ Outline The YSS944 (ADAMB-f)/YSS943 (ADAMB-b)/YSS940 (ADAMB-nd) is an audio decoding digital signal processor that integrates onto a single chip the various digital signal processing functions required for AV amplifiers, etc.
It includes an advanced 32-bit floating-point DSP and is able to decode a variety of audio formats.
[Note] • The contents described in this manual are implemented by downloading boot firmware.
For detailed information about the boot firmware, please contact YAMAHA.
• The YSS943 cannot execute DTS-ES and DTS Neo:6 decoding.
• The YSS940 cannot execute any decoding related to DTS (DTS, DTS-ES, DTS 96/24, and DTS Neo:6).
„ Features • • • • • • • • • • • • Supports various types of decoding up to 7.
1 channels (5.
1/6.
1/7.
1 channels selectable).
5.
1-channel decoding of Dolby Digital (AC-3), DTS, AAC.
6.
1-channel decoding of Dolby Digital EX, DTS-ES.
DTS 96/24 decoding and audio interface clock division/switching functions.
Dolby Pro Logic IIx and DTS Neo:6 decoding Tone control and bass management functions Function modification/expansion by downloading firmware to on-chip memory Lip-sync function that enables synchronization of voice and video with variable voice delay Supports sampling frequencies up to 192 kHz during PCM playback.
1/2 down sampling function when two PCM channels are played back Dolby Digital/DTS/AAC decode information output function (can be read by microprocessor) High-speed/high-accuracy operation by 32-bit floating-point DSP Operating frequency: 180 MHz (178.
176 MHz) Data bus width: 32 bits (24-bit mantissa and 8-bit exponent) Multiplier/adder: 32 bits × 32 bits + 55 bits → 55 bits (47-bit mantissa and 8-bit exponent) No external memory needed (external memory is used when delay is increased.
) Eight general I/O ports On-chip PLL for generation of high-speed internal operating clock Supply voltage: 1.
2 V (core block) and 3.
3 V (pin block) Low power con...


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