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AD9257

Part Number	AD9257
Manufacturer	Analog Devices
Description	1.8V ANALOG-TO-DIGITAL CONVERTER
Published	Oct 14, 2012
Detailed Description	Data Sheet AD9257 Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter FEATURES ► Low power: 55 mW p...
Datasheet	AD9257 PDF File

Overview

Data Sheet AD9257 Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.
8 V Analog-to-Digital Converter FEATURES ► Low power: 55 mW per channel at 65 MSPS with scalable power options ► SNR = 75.
5 dB (to Nyquist) ► SFDR = 91.
6 dBc (to Nyquist) ► DNL = ±0.
6 LSB (typical), INL = ±1.
1 LSB (typical) ► Serial LVDS (ANSI-644, default) ► Low power, reduced signal option (similar to IEEE 1596.
3) ► Data and frame clock outputs ► 650 MHz full power analog bandwidth ► 2 V p-p input voltage range ► 1.
8 V supply operation ► Serial port control ► Full chip and individual channel power-down modes ► Flexible bit orientation ► Built-in and custom digital test pattern generation ► Programmable clock and data alignment ► Programmable output resolution ► Standby mode APPLICATIONS ► Medical imaging and nondestructive ultrasound ► Portable ultrasound and digital beam-forming systems ► Quadrature and diversity radio receivers ► Optical networking ► Test equipment GENERAL DESCRIPTION The AD9257 is an octal, 14-bit, 40 MSPS and 65 MSPS analogto-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.
The ADC requires a single 1.
8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation.
No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate.
A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided.
Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.
FUNCTIONAL BLOCK DIAGRAM Figure 1.
PRODUCT HIGHLIGHTS 1.
Small Footprint.
Eight ADCs are contained in a small, s...

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