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AD9639

Analog Devices
Part Number AD9639
Manufacturer Analog Devices
Description 170 MSPS/210 MSPS Serial Output 1.8 V ADC
Published Nov 11, 2013
Detailed Description Data Sheet Quad, 12-Bit, 170 MSPS/210 MSPS Serial Output 1.8 V ADC AD9639 FEATURES 4 ADCs in one package JESD204 coded...
Datasheet PDF File AD9639 PDF File

AD9639
AD9639

Overview
Data Sheet Quad, 12-Bit, 170 MSPS/210 MSPS Serial Output 1.
8 V ADC AD9639 FEATURES 4 ADCs in one package JESD204 coded serial digital outputs On-chip temperature sensor −95 dB channel-to-channel crosstalk SNR: 65 dBFS with AIN = 85 MHz at 210 MSPS SFDR: 77 dBc with AIN = 85 MHz at 210 MSPS Excellent linearity DNL: ±0.
28 LSB (typical) INL: ±0.
7 LSB (typical) 780 MHz full power analog bandwidth Power dissipation: 325 mW per channel at 210 MSPS 1.
25 V p-p input voltage range, adjustable up to 1.
5 V p-p 1.
8 V supply operation Clock duty cycle stabilizer Serial port interface features Power-down modes Digital test pattern enable Programmable header Programmable pin functions (PGMx, PDWN) APPLICATIONS Communication receivers Cable head end equipment/M-CMTS Broadband radios Wireless infrastructure transceivers Radar/military-aerospace subsystems Test equipment GENERAL DESCRIPTION The AD9639 is a quad, 12-bit, 210 MSPS analog-to-digital converter (ADC) with an on-chip temperature sensor and a high speed serial interface.
It is designed to support the digitizing of high frequency, wide dynamic range signals with an input bandwidth of up to 780 MHz.
The output data is serialized and presented in packet format, consisting of channel-specific information, coded samples, and error code correction.
The ADC requires a single 1.
8 V power supply.
The input clock can be driven differentially with a sine wave, LVPECL, CMOS, or LVDS.
A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.
The on-chip reference eliminates the need for external decoupling and can be adjusted by means of SPI control.
Various power-down and standby modes are supported.
The ADC typically consumes 150 mW per channel with the digital link still in operation when standby operation is enabled.
FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND VIN + A VIN – A VCM A VIN + B VIN – B VCM B VIN + C VIN – C VCM C VIN + D VIN – D VCM D RBIAS TEMPOUT AD9639 BUF ...


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