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74HC374

ON Semiconductor
Part Number 74HC374
Manufacturer ON Semiconductor
Description Octal 3-State Non-Inverting D Flip-Flop
Published May 5, 2014
Detailed Description 74HC374 Octal 3−State Non−Inverting D Flip−Flop High−Performance Silicon−Gate CMOS The 74HC374 is identical in pinout to...
Datasheet PDF File 74HC374 PDF File

74HC374
74HC374

Overview
74HC374 Octal 3−State Non−Inverting D Flip−Flop High−Performance Silicon−Gate CMOS The 74HC374 is identical in pinout to the LS374.
The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge of the clock.
The Output Enable input does not affect the states of the flip−flops, but when Output Enable is high, the outputs are forced to the high−impedance state; thus, data may be stored even when the outputs are not enabled.
The HC374 is identical in function to the HC574A which has the input pins on the opposite side of the package from the output.
This device is similar in function to the HC534A which has inverting outputs.
Features http://onsemi.
com MARKING DIAGRAM 20 20 1 TSSOP−20 DT SUFFIX CASE 948E 1 HC 374 ALYW G G • • • • • • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.
0 to 6.
0 V Low Input Current: 1.
0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No.
7A ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 266 FETs or 66.
5 Equivalent Gates This is a Pb−Free Device HC374 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev.
0 1 Publication Order Number: 74HC374/D http://www.
Datasheet4U.
com 74HC374 PIN ASSIGNMENT LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK 3 4 7 8 13 14 17 18 11 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS OUTPUT ENABLE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q...


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